Searched refs:VecLen (Results 1 – 9 of 9) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 1004 assert(MaskL.size() == VecLen && MaskR.size() == VecLen); in splitMask() 1247 Amount += VecLen; in funnels() 1249 Amount -= VecLen; in funnels() 1566 (void)VecLen; in shuffs1() 1624 shuffles::MaskT MaskL(VecLen), MaskR(VecLen); in shuffs2() 1695 SmallVector<int,256> MaskL(VecLen), MaskR(VecLen); in shuffp2() 1879 if (M < VecLen) { in scalarizeShuffle() 1883 M -= VecLen; in scalarizeShuffle() 2205 int N = VecLen; in expanding() 2239 assert(isPowerOf2_32(VecLen) && Log2_32(VecLen) <= 8); in perfect() [all …]
|
| H A D | HexagonSubtarget.cpp | 239 unsigned VecLen = PowerOf2Ceil(Ty.getVectorNumElements()); in isTypeForHVX() local 240 while (VecLen > 1) { in isTypeForHVX() 241 MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen); in isTypeForHVX() 244 VecLen /= 2; in isTypeForHVX()
|
| H A D | HexagonISelLoweringHVX.cpp | 783 unsigned VecLen = Values.size(); in buildHvxVectorReg() local 790 assert(ElemSize*VecLen == HwLen); in buildHvxVectorReg() 892 if (ExtLen == VecLen || ExtLen == 2*VecLen) { in buildHvxVectorReg() 1083 unsigned VecLen = Values.size(); in buildHvxVectorPred() local 1085 assert(VecLen <= HwLen || VecLen == 8*HwLen); in buildHvxVectorPred() 1100 if (VecLen <= HwLen) { in buildHvxVectorPred() 1104 assert(HwLen % VecLen == 0); in buildHvxVectorPred() 1105 unsigned BitBytes = HwLen / VecLen; in buildHvxVectorPred() 1459 unsigned BitBytes = HwLen / VecLen; in insertHvxSubvectorPred() 2053 assert(HwLen % VecLen == 0); in LowerHvxSelect() [all …]
|
| H A D | HexagonVectorCombine.cpp | 1781 unsigned VecLen = HVC.length(ResizeTy); in processFxpMul() local 1788 for (unsigned V = 0; V != VecLen / ChopLen; ++V) { in processFxpMul() 2341 int VecLen = getSizeOf(Hi); in vlalignb() local 2344 VecLen); in vlalignb() 2347 assert(static_cast<unsigned>(VecLen) == HST.getVectorLength() && in vlalignb() 2353 if (VecLen == 4) { in vlalignb() 2361 if (VecLen == 8) { in vlalignb() 2362 Value *Sub = Builder.CreateSub(getConstInt(VecLen), Amt, "sub"); in vlalignb() 2373 int VecLen = getSizeOf(Lo); in vralignb() local 2384 if (VecLen == 4) { in vralignb() [all …]
|
| H A D | HexagonISelLowering.cpp | 1120 unsigned VecLen = CV->getNumOperands(); in LowerConstantPool() local 1121 assert(isPowerOf2_32(VecLen) && in LowerConstantPool() 1123 for (unsigned i = 0; i < VecLen; ++i) in LowerConstantPool() 2189 unsigned VecLen = VT.getVectorMinNumElements(); in getPreferredVectorAction() local 2192 if (VecLen == 1 || VT.isScalableVector()) in getPreferredVectorAction() 2207 if (!isPowerOf2_32(VecLen)) in getPreferredVectorAction() 2241 unsigned VecLen = AM.size(); in LowerVECTOR_SHUFFLE() local 2264 if (AM[F] >= int(VecLen)) { in LowerVECTOR_SHUFFLE() 2807 unsigned VecLen = VecTy.getVectorNumElements(); in insertVectorPred() local 2812 SDValue Width = DAG.getConstant(8 / VecLen, dl, MVT::i32); in insertVectorPred() [all …]
|
| H A D | HexagonISelDAGToDAG.cpp | 800 unsigned VecLen = ResTy.getSizeInBits(); in SelectVAlign() local 801 if (VecLen == 32) { in SelectVAlign() 831 assert(VecLen == 64); in SelectVAlign()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoopIdiomTransform.cpp | 560 Value *VecLen = Builder.CreateIntrinsic(Intrinsic::vscale, {I64Type}, {}); in expandFindMismatch() local 561 VecLen = Builder.CreateMul(VecLen, ConstantInt::get(I64Type, 16), "", in expandFindMismatch() 610 Value *NewSVEIndexPhi = Builder.CreateAdd(SVEIndexPhi, VecLen, "", in expandFindMismatch()
|
| /freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 20856 unsigned VecLen; in getIntrinsicForHexagonNonClangBuiltin() member 20904 return {F->IntrinsicID, F->VecLen}; in getIntrinsicForHexagonNonClangBuiltin() 20910 unsigned VecLen; in EmitHexagonBuiltinExpr() local 20911 std::tie(ID, VecLen) = getIntrinsicForHexagonNonClangBuiltin(BuiltinID); in EmitHexagonBuiltinExpr() 20979 auto V2Q = [this, VecLen] (llvm::Value *Vec) { in EmitHexagonBuiltinExpr() 20980 Intrinsic::ID ID = VecLen == 128 ? Intrinsic::hexagon_V6_vandvrt_128B in EmitHexagonBuiltinExpr() 20985 auto Q2V = [this, VecLen] (llvm::Value *Pred) { in EmitHexagonBuiltinExpr() 20986 Intrinsic::ID ID = VecLen == 128 ? Intrinsic::hexagon_V6_vandqrt_128B in EmitHexagonBuiltinExpr()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 10937 SDValue VecLen = in lowerVPReverseExperimental() local 10940 DAG.getUNDEF(IndicesVT), VecLen, EVL); in lowerVPReverseExperimental()
|