Searched refs:Vec2 (Results 1 – 6 of 6) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/clang/lib/AST/ |
| H A D | ASTStructuralEquivalence.cpp | 946 const auto *Vec2 = cast<DependentSizedExtVectorType>(T2); in IsStructurallyEquivalent() local
948 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
951 Vec2->getElementType())) in IsStructurallyEquivalent()
958 const auto *Vec2 = cast<DependentVectorType>(T2); in IsStructurallyEquivalent() local
959 if (Vec1->getVectorKind() != Vec2->getVectorKind()) in IsStructurallyEquivalent()
962 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
965 Vec2->getElementType())) in IsStructurallyEquivalent()
973 const auto *Vec2 = cast<VectorType>(T2); in IsStructurallyEquivalent() local
975 Vec2->getElementType())) in IsStructurallyEquivalent()
977 if (Vec1->getNumElements() != Vec2->getNumElements()) in IsStructurallyEquivalent()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1899 SDValue Vec2; in ExpandBVWithShuffles() local
1901 Vec2 = IntermedVals[1].first; in ExpandBVWithShuffles()
1903 Vec2 = DAG.getUNDEF(VT); in ExpandBVWithShuffles()
1912 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBVWithShuffles()
2014 SDValue Vec2; in ExpandBUILD_VECTOR() local
2016 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
2018 Vec2 = DAG.getUNDEF(VT); in ExpandBUILD_VECTOR()
2021 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBUILD_VECTOR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 456 Value *Vec2 = nullptr; in isFixedVectorShuffle() local
488 } else if (!Vec2 || Vec2 == Vec) { in isFixedVectorShuffle()
489 Vec2 = Vec; in isFixedVectorShuffle()
505 if (CommonShuffleMode == Select && Vec2) in isFixedVectorShuffle()
509 return Vec2 ? TargetTransformInfo::SK_PermuteTwoSrc in isFixedVectorShuffle()
10881 Value *Vec2 = nullptr; in processBuildVector() local
10902 assert((!Vec2 || Vec2 == EI->getVectorOperand()) && in processBuildVector()
10904 Vec2 = VecOp; in processBuildVector()
10908 if (Vec2) { in processBuildVector()
10911 isGuaranteedNotToBePoison(Vec1) && isGuaranteedNotToBePoison(Vec2); in processBuildVector()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrMMA.td | 1078 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));
1094 Extracts.Vec2>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Bitcode/Reader/ |
| H A D | BitcodeReader.cpp | 5216 Value *Vec1, *Vec2, *Mask; in parseFunctionBody() local
5221 Vec2, CurBB)) in parseFunctionBody()
5227 if (!Vec1->getType()->isVectorTy() || !Vec2->getType()->isVectorTy()) in parseFunctionBody()
5230 I = new ShuffleVectorInst(Vec1, Vec2, Mask); in parseFunctionBody()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 14148 SDValue Vec2 = Op2.getOperand(0); in performFMACombine() local
14173 if (Vec1 == Vec2 || Vec3 == Vec4) in performFMACombine()
14176 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16) in performFMACombine()
14179 if ((Vec1 == Vec3 && Vec2 == Vec4) || in performFMACombine()
14180 (Vec1 == Vec4 && Vec2 == Vec3)) { in performFMACombine()
14181 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc, in performFMACombine()
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