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Searched refs:Vd (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2854 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2890 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2927 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2935 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2946 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2954 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2964 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3192 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3200 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
5253 // Vq, Vd, Vd[0-7], Idx[0-3]
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H A DARMInstrCDE.td313 bits<5> Vd;
315 let Inst{22} = Vd{0};
323 bits<5> Vd;
325 let Inst{22} = Vd{4};
374 bits<5> Vd;
378 let Inst{22} = Vd{0};
387 bits<5> Vd;
391 let Inst{22} = Vd{4};
442 bits<5> Vd;
446 let Inst{22} = Vd{0};
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H A DARMInstrFormats.td2235 bits<5> Vd;
2305 bits<5> Vd;
2331 bits<5> Vd;
2346 bits<5> Vd;
2384 bits<5> Vd;
2406 bits<5> Vd;
2438 bits<5> Vd;
2455 bits<5> Vd;
2483 bits<5> Vd;
2504 bits<5> Vd;
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H A DARMInstrVFP.td1801 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1814 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
/freebsd-14.2/tests/sys/cddl/zfs/tests/acl/nontrivial/
H A Dzfs_acl_chmod_inherit_003_pos.ksh295 $LS -Vd $basedir
296 $LS -Vd $node
312 $LS -Vd $basedir
313 $LS -Vd $node
337 $LS -Vd $basedir
338 $LS -Vd $node
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyTIL.h380 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
381 Flags = Vd.kind(); in Variable()
675 Function(Variable *Vd, SExpr *Bd) in Function() argument
677 Vd->setKind(Variable::VK_Fun); in Function()
682 Vd->setKind(Variable::VK_Fun); in Function()
726 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
729 Vd->setKind(Variable::VK_SFun); in SFunction()
730 Vd->Definition = this; in SFunction()
737 Vd->Definition = this; in SFunction()
1866 Let(Variable *Vd, SExpr *Bd) : SExpr(COP_Let), VarDecl(Vd), Body(Bd) { in Let() argument
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/freebsd-14.2/contrib/llvm-project/clang/lib/Analysis/
H A DThreadSafety.cpp264 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
296 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
302 void checkBeforeAfter(const ValueDecl* Vd,
1091 for (const auto *At : Vd->attrs()) { in insertAttrExprs()
1119 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1135 auto It = BMap.find(Vd); in getBeforeInfoForDecl()
1138 Info = insertAttrExprs(Vd, Analyzer); in getBeforeInfoForDecl()
1155 if (!Vd) in checkBeforeAfter()
1180 if (!CycMap.contains(Vd)) { in checkBeforeAfter()
1181 CycMap.insert(std::make_pair(Vd, true)); in checkBeforeAfter()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td5030 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
5032 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
5130 // concat_vectors(Vd, trunc(smin(smax Vm, -128), 127) ~> SQXTN2(Vd, Vn)
5143 // concat_vectors(Vd, trunc(smin(smax Vm, -32768), 32767) ~> SQXTN2(Vd, Vn)
7005 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
7006 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
7007 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
7008 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
7010 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
7011 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
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H A DAArch64SchedPredNeoverse.td80 // MOVI Vd.2D, #0
H A DAArch64SchedPredicates.td326 [// MOVI Vd, #0
331 // MOVI Vd, #0, LSL #0
H A DAArch64InstrFormats.td8100 bits<5> Vd;
8119 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
8121 bits<5> Vd;
11634 bits<5> Vd;
11652 : CryptoRRTied<op0, op1, asm, "{\t$Vd.2d, $Vn.2d|.2d\t$Vd, $Vn}">;
11654 : CryptoRRTied<op0, op1, asm, "{\t$Vd.4s, $Vn.4s|.4s\t$Vd, $Vn}">;
11669 "{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "">;
11672 "{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
11675 "{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "">;
11678 "{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
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H A DAArch64SchedCyclone.td327 // FMOVv2f64ns Vd.2d, #0.0
336 // ORR.16b Vd,Vn,Vn
637 // Vd is read 5 cycles after issuing the vector load.
H A DAArch64InstrGISel.td462 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
H A DSVEInstrFormats.td5445 asm, "\t$Vd, $Pg, $Zn",
5449 bits<5> Vd;
5458 let Inst{4-0} = Vd;
7010 bits<5> Vd;
7019 let Inst{4-0} = Vd;
8389 bits<5> Vd;
8399 let Inst{4-0} = Vd;
9950 bits<5> Vd;
9960 let Inst{4-0} = Vd;
10185 bits<5> Vd;
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCVXsf.td30 … !if(HasDst, [], [ImmArg<ArgIndex<2>>]), // Vd or bit<11-7>
49 … !if(HasDst, [], [ImmArg<ArgIndex<1>>]), // Vd or bit<11-7>
/freebsd-14.2/sys/contrib/openzfs/tests/zfs-tests/tests/functional/acl/
H A Dacl_common.kshlib61 ls -Vd $obj | awk '(NR != 1) {print $0}'
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp858 MaskT Vd(Len); in vpack() local
863 Vd[i * Size + b] = Vv[(2 * i + Odd) * Size + b]; in vpack()
868 return Vd; in vpack()
873 MaskT Vd(Len); in vshuff() local
881 return Vd; in vshuff()
892 MaskT Vd(Len); in vdealb4w() local
894 Vd[0 * (Len / 4) + i] = Vv[4 * i + 0]; in vdealb4w()
895 Vd[1 * (Len / 4) + i] = Vv[4 * i + 2]; in vdealb4w()
896 Vd[2 * (Len / 4) + i] = Vu[4 * i + 0]; in vdealb4w()
897 Vd[3 * (Len / 4) + i] = Vu[4 * i + 2]; in vdealb4w()
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H A DHexagonPseudo.td432 class Vsplatr_template : InstHexagon<(outs HvxVR:$Vd), (ins IntRegs:$Rs),
440 class Vsplati_template : InstHexagon<(outs HvxVR:$Vd), (ins s32_0Imm:$Val),
506 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
H A DHexagonInstrInfo.cpp1277 Register Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1278 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1279 .addReg(Vd, RegState::Undef) in expandPostRAPseudo()
1280 .addReg(Vd, RegState::Undef); in expandPostRAPseudo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1786 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1790 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1791 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1811 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1815 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1816 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
6015 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTD() local
6016 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTD()
6074 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTQ() local
6075 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTQ()
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/freebsd-14.2/tests/sys/cddl/zfs/tests/acl/
H A Dacl_common.kshlib83 $LS -Vd $obj | $NAWK '(NR != 1) {print $0}'
/freebsd-14.2/contrib/file/tests/
H A DHWP97.hwp.testfile8 …L�rQ9L�#������ 9�}\��q]ɰ^6�G�����] ��Փ3Q׻�"����l����a�ˤ�&W:Ln�VdR�u�;*g�^���|�N���…
/freebsd-14.2/contrib/llvm-project/llvm/tools/llvm-objdump/
H A DMachODump.cpp10038 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); in PrintLoadCommands() local
10039 PrintVersionMinLoadCommand(Vd); in PrintLoadCommands()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Driver/
H A DOptions.td8504 def dxc_disable_validation : DXCFlag<"Vd">,