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Searched refs:VTSize (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp199 unsigned VTSize = 4; in EmitTargetCodeForMemcpy() local
237 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
238 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
258 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
265 SrcOff += VTSize; in EmitTargetCodeForMemcpy()
266 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
274 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
280 DstOff += VTSize; in EmitTargetCodeForMemcpy()
281 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
H A DARMCallLowering.cpp76 unsigned VTSize = VT.getSimpleVT().getSizeInBits(); in isSupportedType() local
78 if (VTSize == 64) in isSupportedType()
82 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32; in isSupportedType()
H A DARMISelLowering.cpp8251 uint64_t VTSize = VT.getFixedSizeInBits(); in ReconstructShuffle() local
8252 if (SrcVTSize == VTSize) in ReconstructShuffle()
8258 unsigned NumSrcElts = VTSize / EltVT.getFixedSizeInBits(); in ReconstructShuffle()
8261 if (SrcVTSize < VTSize) { in ReconstructShuffle()
8262 if (2 * SrcVTSize != VTSize) in ReconstructShuffle()
8272 if (SrcVTSize != 2 * VTSize) in ReconstructShuffle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1094 unsigned VTSize = VT.getScalarSizeInBits(); in earlyExpandDIVFIX() local
1116 assert(SatW <= VTSize && in earlyExpandDIVFIX()
4091 unsigned VTSize = VT.getScalarSizeInBits(); in ExpandIntRes_MULFIX() local
4112 APInt MinVal = APInt::getSignedMinValue(VTSize); in ExpandIntRes_MULFIX()
4113 APInt MaxVal = APInt::getSignedMaxValue(VTSize); in ExpandIntRes_MULFIX()
4126 APInt MaxVal = APInt::getMaxValue(VTSize); in ExpandIntRes_MULFIX()
4193 if (Scale == VTSize) in ExpandIntRes_MULFIX()
4227 } else if (Scale < VTSize) { in ExpandIntRes_MULFIX()
4247 unsigned OverflowBits = VTSize - Scale + 1; in ExpandIntRes_MULFIX()
4279 } else if (Scale < VTSize) { in ExpandIntRes_MULFIX()
[all …]
H A DTargetLowering.cpp233 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering() local
234 while (VTSize > Size) { in findOptimalMemOpLowering()
271 VTSize = Size; in findOptimalMemOpLowering()
274 VTSize = NewVTSize; in findOptimalMemOpLowering()
282 Size -= VTSize; in findOptimalMemOpLowering()
10170 unsigned VTSize = VT.getScalarSizeInBits(); in expandFixedPointMul() local
10200 APInt MaxVal = APInt::getMaxValue(VTSize); in expandFixedPointMul()
10206 assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && in expandFixedPointMul()
10229 if (Scale == VTSize) in expandFixedPointMul()
10250 APInt MaxVal = APInt::getMaxValue(VTSize); in expandFixedPointMul()
[all …]
H A DSelectionDAG.cpp7524 if (VTSize > Size) { in getMemcpyLoadsAndStores()
7528 SrcOff -= VTSize - Size; in getMemcpyLoadsAndStores()
7529 DstOff -= VTSize - Size; in getMemcpyLoadsAndStores()
7589 SrcOff += VTSize; in getMemcpyLoadsAndStores()
7590 DstOff += VTSize; in getMemcpyLoadsAndStores()
7591 Size -= VTSize; in getMemcpyLoadsAndStores()
7726 SrcOff += VTSize; in getMemmoveLoadsAndStores()
7740 DstOff += VTSize; in getMemmoveLoadsAndStores()
7834 if (VTSize > Size) { in getMemsetStores()
7838 DstOff -= VTSize - Size; in getMemsetStores()
[all …]
H A DDAGCombiner.cpp19690 TypeSize VTSize = VT.getSizeInBits(); in TransformFPLoadStorePair() local
19694 if (VTSize.isScalable()) in TransformFPLoadStorePair()
19698 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue()); in TransformFPLoadStorePair()
22740 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle() local
22750 if ((VTSize % InVT1Size == 0) && InVT1 == InVT2) { in createBuildVecShuffle()
22753 unsigned NumConcats = VTSize / InVT1Size; in createBuildVecShuffle()
22760 } else if (InVT1Size == VTSize * 2) { in createBuildVecShuffle()
22796 } else if (InVT2Size * 2 == VTSize && InVT1Size == VTSize) { in createBuildVecShuffle()
22800 } else if (InVT1Size / VTSize > 1 && InVT1Size % VTSize == 0) { in createBuildVecShuffle()
22822 ShuffleNumElems = InVT1Size / VTSize * NumElems; in createBuildVecShuffle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4043 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorFP_TO_INT() local
4045 if (VTSize < InVTSize) { in LowerVectorFP_TO_INT()
4060 if (VTSize > InVTSize) { in LowerVectorFP_TO_INT()
4280 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorINT_TO_FP() local
4282 if (VTSize < InVTSize) { in LowerVectorINT_TO_FP()
4298 if (VTSize > InVTSize) { in LowerVectorINT_TO_FP()
10663 if (VTSize == 16) in getRegForInlineAsmConstraint()
10665 if (VTSize == 32) in getRegForInlineAsmConstraint()
10667 if (VTSize == 64) in getRegForInlineAsmConstraint()
10669 if (VTSize == 128) in getRegForInlineAsmConstraint()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp6343 uint64_t VTSize = DL->getTypeStoreSizeInBits(FixedVectorType::get(EltTy, N)); in canMapToVector() local
6344 if (VTSize < MinVecRegSize || VTSize > MaxVecRegSize || in canMapToVector()
6345 VTSize != DL->getTypeStoreSizeInBits(T)) in canMapToVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp18994 unsigned VTSize = VT.getSizeInBits(); in lowerFPToIntToFP() local
18997 MVT VecVT = MVT::getVectorVT(VT, 128 / VTSize); in lowerFPToIntToFP()
19003 IntSize != VTSize ? X86ISD::CVTSI2P : (unsigned)ISD::SINT_TO_FP; in lowerFPToIntToFP()