Home
last modified time | relevance | path

Searched refs:VTList (Results 1 – 16 of 16) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp685 ID.AddPointer(VTList.VTs); in AddNodeIDValueTypes()
709 AddNodeIDValueTypes(ID, VTList); in AddNodeIDNode()
8353 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) { in getMemIntrinsicNode()
9839 if (VTList.NumVTs == 1) in getNode()
9855 assert(VTList.VTs[0].isInteger() && VTList.VTs[1].isInteger() && in getNode()
9870 if (VTList.VTs[0].isVector() && in getNode()
9895 assert(VTList.VTs[0].isInteger() && VTList.VTs[0] == VTList.VTs[1] && in getNode()
9925 assert(VTList.VTs[0].isFloatingPoint() && VTList.VTs[1].isInteger() && in getNode()
9995 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) { in getNode()
10640 if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) { in getNodeIfExists()
[all …]
H A DLegalizeIntegerTypes.cpp3238 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); in ExpandIntRes_ADDSUB() local
3240 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
3242 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3244 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
3246 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3259 SDVTList VTList = DAG.getVTList(NVT, OvfVT); in ExpandIntRes_ADDSUB() local
3348 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
3350 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
3352 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
3354 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
[all …]
H A DSelectionDAGISel.cpp2618 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, in MorphNode() argument
2639 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops); in MorphNode()
3941 SDVTList VTList; in SelectCodeCommon() local
3943 VTList = CurDAG->getVTList(VTs[0]); in SelectCodeCommon()
3945 VTList = CurDAG->getVTList(VTs[0], VTs[1]); in SelectCodeCommon()
3947 VTList = CurDAG->getVTList(VTs); in SelectCodeCommon()
4002 VTList, Ops); in SelectCodeCommon()
4021 Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList, in SelectCodeCommon()
H A DScheduleDAGSDNodes.cpp149 SDVTList VTList = DAG->getVTList(VTs); in CloneNodeWithValues() local
157 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops); in CloneNodeWithValues()
H A DTargetLowering.cpp7699 SDVTList VTList = DAG.getVTList(HiLoVT, SetCCType); in expandDIVREMByConstant() local
7700 Sum = DAG.getNode(ISD::UADDO, dl, VTList, LL, LH); in expandDIVREMByConstant()
7701 Sum = DAG.getNode(ISD::UADDO_CARRY, dl, VTList, Sum, in expandDIVREMByConstant()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1121 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
1127 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
1150 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList);
1151 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N);
1288 SDVTList VTList, ArrayRef<SDValue> Ops,
1296 unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1303 unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1310 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1729 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
1731 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
[all …]
H A DSelectionDAGISel.h471 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp230 SDVTList VTList = CurDAG->getVTList(VT, MVT::Other); in matchLoadD16FromBuildVector() local
246 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdHi), VTList, in matchLoadD16FromBuildVector()
264 SDVTList VTList = CurDAG->getVTList(VT, MVT::Other); in matchLoadD16FromBuildVector() local
280 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdLo), VTList, in matchLoadD16FromBuildVector()
843 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue); in SelectADD_SUB_I64() local
857 AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args); in SelectADD_SUB_I64()
860 AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args); in SelectADD_SUB_I64()
867 SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs); in SelectADD_SUB_I64()
H A DSIISelLowering.cpp5725 VTList, Ops, M->getMemoryVT(), in adjustLoadValueType()
5771 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other); in lowerIntrinsicLoad() local
7903 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue}); in lowerSBuffer() local
9129 EVT VT = VTList.VTs[0]; in getMemIntrinsicNode()
9131 assert(VTList.NumVTs == 2 || VTList.NumVTs == 3); in getMemIntrinsicNode()
9132 bool IsTFE = VTList.NumVTs == 3; in getMemIntrinsicNode()
10352 return DAG.getNode(Opcode, SL, VTList, in getFPBinOp()
10374 return DAG.getNode(Opcode, SL, VTList, in getFPTernOp()
13907 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1); in performAddCombine() local
13910 return DAG.getNode(Opc, SL, VTList, Args); in performAddCombine()
[all …]
H A DSIISelLowering.h128 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2654 SDVTList VTList = DAG.getVTList(VT, VT); in lowerShiftRightParts() local
2657 DL, VTList, Cond, ShiftRightHi, in lowerShiftRightParts()
2676 SDVTList VTList = DAG.getVTList(VT, MVT::Other); in createLoadLR() local
2683 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createLoadLR()
2757 SDVTList VTList = DAG.getVTList(MVT::Other); in createStoreLR() local
2764 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createStoreLR()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp85 TypeSetByHwMode::TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList) { in TypeSetByHwMode() argument
87 if (!VTList.empty()) in TypeSetByHwMode()
88 AddrSpace = VTList[0].PtrAddrSpace; in TypeSetByHwMode()
90 for (const ValueTypeByHwMode &VVT : VTList) in TypeSetByHwMode()
H A DCodeGenDAGPatterns.h206 TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4624 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); in lowerATOMIC_LOAD_OP() local
4627 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops, in lowerATOMIC_LOAD_OP()
4707 SDVTList VTList = DAG.getVTList(WideVT, MVT::i32, MVT::Other); in lowerATOMIC_CMP_SWAP() local
4711 VTList, Ops, NarrowVT, MMO); in lowerATOMIC_CMP_SWAP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5686 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in OptimizeVFPBrcond() local
5688 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops); in OptimizeVFPBrcond()
5803 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in LowerBR_CC() local
5805 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
5809 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp10248 SDVTList VTList = Op->getVTList(); in lowerVectorStrictFSetcc() local
10251 SDValue Tmp1 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc()
10253 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, in lowerVectorStrictFSetcc()
10266 SDValue OEQ = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc()