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Searched refs:VT2 (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h90 const PassNameParser::OptionInfo *VT2) { in ValCompare() argument
91 return VT1->Name.compare(VT2->Name); in ValCompare()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h144 bool isTruncateFree(EVT VT1, EVT VT2) const override;
148 bool isZExtFree(EVT VT1, EVT VT2) const override;
149 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DBPFISelLowering.cpp206 bool BPFTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
207 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
210 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
222 bool BPFTargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
223 if (!getHasAlu32() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
226 unsigned NumBits2 = VT2.getSizeInBits(); in isZExtFree()
230 bool BPFTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
232 if (Val.getOpcode() == ISD::LOAD && VT1.isSimple() && VT2.isSimple()) { in isZExtFree()
234 MVT MT2 = VT2.getSimpleVT().SimpleTy; in isZExtFree()
239 return TargetLoweringBase::isZExtFree(Val, VT2); in isZExtFree()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h117 bool isTruncateFree(EVT VT1, EVT VT2) const override;
128 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1394 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
1395 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1398 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
1406 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
1408 return false && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h640 SDVTList getVTList(EVT VT1, EVT VT2);
641 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
642 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
1667 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1669 EVT VT2, ArrayRef<SDValue> Ops);
1671 EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
1673 EVT VT2, SDValue Op1, SDValue Op2);
1703 EVT VT2, SDValue Op1, SDValue Op2);
1707 EVT VT2, ArrayRef<SDValue> Ops);
1714 EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
[all …]
H A DTargetLowering.h1685 MVT VT2; variable
1687 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
2859 virtual bool isTruncateFree(SDValue Val, EVT VT2) const { in isTruncateFree() argument
2861 return isTruncateFree(Val.getValueType(), VT2); in isTruncateFree()
2947 virtual bool isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree() argument
2948 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h95 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DXCoreISelLowering.cpp174 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
180 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h226 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DLoongArchISelLowering.cpp4919 bool LoongArchTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
4931 return TargetLowering::isZExtFree(Val, VT2); in isZExtFree()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h659 bool isTruncateFree(EVT VT1, EVT VT2) const override;
664 bool isZExtFree(EVT VT1, EVT VT2) const override;
665 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DAArch64ISelLowering.cpp14719 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
14720 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
14723 uint64_t NumBits2 = VT2.getFixedSizeInBits(); in isTruncateFree()
14763 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
14764 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
14767 unsigned NumBits2 = VT2.getSizeInBits(); in isZExtFree()
14771 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
14773 if (isZExtFree(VT1, VT2)) { in isZExtFree()
14782 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() && in isZExtFree()
27071 MVT VT2; in getNumRegistersForCallingConv() local
[all …]
H A DAArch64InstrInfo.td8361 foreach VT2 = [ v8i8, v4i16, v4f16, v4bf16, v2i32, v2f32, v1i64, v1f64, f64 ] in
8362 def : Pat<(VT (AArch64NvCast (VT2 FPR64:$src))),
8367 foreach VT2 = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in
8368 def : Pat<(VT (AArch64NvCast (VT2 FPR128:$src))),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1341 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1354 bool isZExtFree(EVT VT1, EVT VT2) const override;
1355 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DX86ISelLowering.cpp33690 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
33691 if (!VT1.isScalarInteger() || !VT2.isScalarInteger()) in isTruncateFree()
33694 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
33703 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
33705 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget.is64Bit(); in isZExtFree()
33708 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
33710 if (isZExtFree(VT1, VT2)) in isZExtFree()
33717 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
37781 MVT VT2 = V2.getSimpleValueType(); in combineX86ShuffleChain() local
37795 bool FloatDomain = VT1.isFloatingPoint() || VT2.isFloatingPoint() || in combineX86ShuffleChain()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp10061 ID.AddInteger(VT2.getRawBits()); in getVTList()
10068 Array[1] = VT2; in getVTList()
10079 ID.AddInteger(VT2.getRawBits()); in getVTList()
10087 Array[1] = VT2; in getVTList()
10099 ID.AddInteger(VT2.getRawBits()); in getVTList()
10108 Array[1] = VT2; in getVTList()
10320 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
10326 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
10340 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
10528 SDVTList VTs = getVTList(VT1, VT2); in getMachineNode()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1021 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1023 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DPPCISelLowering.cpp17183 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
17184 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
17187 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
17191 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
17208 return TargetLowering::isZExtFree(Val, VT2); in isZExtFree()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h450 bool isZExtFree(SDValue Val, EVT VT2) const override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h149 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DHexagonISelLowering.cpp2146 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
2147 if (!VT1.isSimple() || !VT2.isSimple()) in isTruncateFree()
2149 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h463 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DARMInstrMVE.td4499 foreach VT2 = [ v2i1, v4i1, v8i1, v16i1 ] in
4500 def : Pat<(VT (predicate_cast (VT2 VCCR:$src))),
4501 (VT (COPY_TO_REGCLASS (VT2 VCCR:$src), VCCR))>;
4518 foreach VT2 = [ v16i8, v8i16, v8f16, v4i32, v4f32, v2i64, v2f64 ] in
4519 def : Pat<(VT (ARMVectorRegCastImpl (VT2 MQPR:$src))),
H A DARMInstrNEON.td7770 foreach VT2 = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in
7771 def : Pat<(VT (ARMVectorRegCastImpl (VT2 QPR:$src))), (VT QPR:$src)>;
7774 foreach VT2 = [ v8i8, v4i16, v4f16, v4bf16, v2i32, v2f32, v1i64, f64 ] in
7775 def : Pat<(VT (ARMVectorRegCastImpl (VT2 DPR:$src))), (VT DPR:$src)>;

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