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Searched refs:VSCALE (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1321 VSCALE, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp180 case ISD::VSCALE: return "vscale"; in getOperationName()
H A DSelectionDAG.cpp2010 return getNode(ISD::VSCALE, DL, VT, getConstant(MulImm, DL, VT)); in getVScale()
3168 case ISD::VSCALE: { in computeKnownBits()
4222 if (Val.getOpcode() == ISD::VSCALE && in isKnownToBeAPowerOfTwo()
5780 if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes) in getNode()
5851 case ISD::VSCALE: in getNode()
6635 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
6703 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
H A DLegalizeIntegerTypes.cpp113 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; in PromoteIntegerResult()
2773 case ISD::VSCALE: in ExpandIntegerResult()
H A DDAGCombiner.cpp2983 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2991 N0.getOperand(1).getOpcode() == ISD::VSCALE && in visitADD()
2992 N1.getOpcode() == ISD::VSCALE) { in visitADD()
4098 if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) { in visitSUB()
4541 if (N0.getOpcode() == ISD::VSCALE && NC1) { in visitMUL()
10123 if (N0.getOpcode() == ISD::VSCALE && N1C) { in visitSHL()
H A DSelectionDAGBuilder.cpp4194 ISD::VSCALE, dl, VScaleTy, in visitGetElementPtr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp646 setOperationAction(ISD::VSCALE, XLenVT, Custom); in RISCVTargetLowering()
648 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in RISCVTargetLowering()
6022 case ISD::VSCALE: { in LowerOperation()
10910 SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT, in lowerVPReverseExperimental()
18163 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerFormalArguments()
18450 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td354 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp6928 if (VScale.getOpcode() != ISD::VSCALE) in SelectAddrModeIndexedSVE()
H A DAArch64ISelLowering.cpp1639 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in AArch64TargetLowering()
6318 case ISD::VSCALE: in LowerOperation()
18031 if (VS.getOpcode() != ISD::VSCALE) in performLastTrueTestVectorCombine()