Searched refs:VROR (Results 1 – 6 of 6) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 961 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg() 968 HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, Sm}); in buildHvxVectorReg() 979 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg() 980 HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, Sm}); in buildHvxVectorReg() 1070 Vec = DAG.getNode(HexagonISD::VROR, dl, ByteTy, Vec, S4); in createHvxPrefixPred() 1411 SingleV = DAG.getNode(HexagonISD::VROR, dl, SingleTy, SingleV, IdxV); in insertHvxSubvectorReg() 1425 SingleV = DAG.getNode(HexagonISD::VROR, dl, SingleTy, SingleV, in insertHvxSubvectorReg() 1754 Res = DAG.getNode(HexagonISD::VROR, dl, ByteTy, Res, S); in LowerHvxConcatVectors() 3631 case HexagonISD::VROR: { in PerformHvxDAGCombine() 3632 if (Ops[0].getOpcode() == HexagonISD::VROR) { in PerformHvxDAGCombine() [all …]
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| H A D | HexagonISelLowering.h | 75 VROR, enumerator
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| H A D | HexagonISelDAGToDAG.cpp | 928 case HexagonISD::VROR: return SelectHvxRor(N); in Select()
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| H A D | HexagonISelLowering.cpp | 1925 case HexagonISD::VROR: return "HexagonISD::VROR"; in getTargetNodeName()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPInstrPatternsVec.td | 620 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "or", "VROR">;
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| H A D | VEInstrVec.td | 1396 // Section 8.14.8 - VROR (Vector Reduction Or) 1397 defm VROR : RVF1m<"vror", 0x98, V64, VM>;
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