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Searched refs:VR1 (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_avx512bw.c52 #define VR1(r...) VR1_(r) macro
80 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
88 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
124 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
131 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
144 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
197 "vpaddb %" VR1(r)", %" VR1(r)", %" VR1(r) "\n" \
252 "vpandq %%" _0f ", %%" VR1(r) ", %%" VR1(r) "\n" \
270 "vpshufb %%" VR1(r) ", %%" _ltmul ", %%" VR1(r) "\n"\
274 "vpxorq %%" _tb ", %%" VR1(r) ", %%" VR1(r) "\n" \
[all …]
H A Dvdev_raidz_math_avx2.c48 #define VR1(r...) VR1_(r) macro
77 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
85 "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
121 "vmovdqa %" VR1(r) ", %" VR5(r) "\n" \
128 "vmovdqa %" VR1(r) ", %" VR3(r)); \
199 "vpaddb %" VR1(r)", %" VR1(r)", %" VR1(r) "\n" \
203 "vpxor %ymm13, %" VR1(r)", %" VR1(r)); \
254 "vpand %%" _0f ", %%" VR1(r) ", %%" VR1(r) "\n" \
272 "vpshufb %%" VR1(r) ", %%" _ltmul ", %%" VR1(r) "\n"\
276 "vpxor %%" _tb ", %%" VR1(r) ", %%" VR1(r) "\n" \
[all …]
H A Dvdev_raidz_math_ssse3.c49 #define VR1(r...) VR1_(r) macro
78 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
86 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
100 "pxor %" VR1(r) ", %" VR5(r) "\n" \
107 "pxor %" VR1(r) ", %" VR3(r)); \
129 "movdqa %" VR1(r) ", %" VR3(r)); \
196 "pcmpgtb %" VR1(r)", %xmm13\n" \
200 "paddb %" VR1(r)", %" VR1(r) "\n" \
202 "pxor %xmm13, %" VR1(r)); \
252 "psraw $0x4, %%" VR1(r) "\n" \
[all …]
H A Dvdev_raidz_math_powerpc_altivec_common.h147 "vxor " VR1(r) "," VR1(r) ",20\n" \
177 "vxor " VR1(r) "," VR1(r) ",20\n" \
192 "vxor " VR1(r) "," VR1(r) ",20\n" \
233 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
246 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
254 "vxor " VR1(r) "," VR1(r) "," VR1(r) "\n" \
421 "vaddubm " VR1(r) "," VR1(r) "," VR1(r) "\n" \
425 "vxor " VR1(r) ",18," VR1(r) "\n" \
439 "vaddubm " VR1(r) "," VR1(r) "," VR1(r) "\n" \
441 "vxor " VR1(r) ",18," VR1(r) "\n" \
[all …]
H A Dvdev_raidz_math_aarch64_neon_common.h150 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
180 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
195 "eor " VR1(r) ".16b," VR1(r) ".16b,v20.16b\n" \
236 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
249 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
257 "eor " VR1(r) ".16b," VR1(r) ".16b," VR1(r) ".16b\n" \
420 "shl " VR1(r) ".16b," VR1(r) ".16b,#1\n" \
424 "eor " VR1(r) ".16b,v18.16b," VR1(r) ".16b\n" \
438 "shl " VR1(r) ".16b," VR1(r) ".16b,#1\n" \
440 "eor " VR1(r) ".16b,v18.16b," VR1(r) ".16b\n" \
[all …]
H A Dvdev_raidz_math_avx512f.c51 #define VR1(r...) VR1_(r) macro
94 "vpxorq 0x40(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
108 "vpxorq %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
115 "vpxorq %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
130 "vmovdqa64 %" VR1(r) ", %" VR5(r) "\n" \
137 "vmovdqa64 %" VR1(r) ", %" VR3(r)); \
148 "vmovdqa64 0x40(%[SRC]), %%" VR1(r) "\n" \
162 "vmovdqa64 %%" VR1(r) ", 0x40(%[DST])\n" \
186 "vpandq %" VR1(r)", %zmm30, %zmm25\n" \
194 "vpsllq $1, %" VR1(r)", %" VR1(r) "\n" \
[all …]
H A Dvdev_raidz_math_sse2.c50 #define VR1(r...) VR1_(r, 1, 2, 3, 4, 5, 6) macro
70 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
78 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
94 "pxor %" VR1(r) ", %" VR5(r) "\n" \
101 "pxor %" VR1(r) ", %" VR3(r)); \
105 "pxor %" VR0(r) ", %" VR1(r)); \
118 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
125 "movdqa %" VR1(r) ", %" VR3(r)); \
129 "movdqa %" VR0(r) ", %" VR1(r)); \
225 _MUL2_x2(VR0(r), VR1(r)); \
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp223 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
224 return operator[](VR1) < operator[](VR2); in operator ()()
298 bool operator() (unsigned VR1, unsigned VR2) const;
316 bool operator() (unsigned VR1, unsigned VR2) const;
327 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
337 if (VR1 == VR2) in operator ()()
340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
351 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
355 if (VR1 == VR2) in operator ()()
357 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
277 .addReg(VR1, RegState::Kill); in expandCopyACC()
H A DMipsSEISelLowering.cpp3060 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3061 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3069 .addReg(VR1) in emitBPOSGE32()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp3488 const MCPhysReg ArgVRs[] = {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,