Home
last modified time | relevance | path

Searched refs:VPR (Results 1 – 20 of 20) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp74 if (CmpMI->modifiesRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
76 if (CmpMI->readsRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
134 if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR)) in IsVPRDefinedOrKilledByBlock()
H A DMVETPAndVPTOptimisationsPass.cpp931 Register VPR = Instr.getOperand(PIdx + 1).getReg(); in ReplaceConstByVPNOTs() local
932 if (!VPR.isVirtual()) in ReplaceConstByVPNOTs()
936 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs()
960 if (LastVPTReg != 0 && LastVPTReg != VPR && LastVPTImm == Imm) { in ReplaceConstByVPNOTs()
962 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
968 VPR = LastVPTReg; in ReplaceConstByVPNOTs()
980 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
987 VPR = NewVPR; in ReplaceConstByVPNOTs()
991 LastVPTReg = VPR; in ReplaceConstByVPNOTs()
H A DARMLowOverheadLoops.cpp90 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR; in isVectorPredicated()
94 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1; in isVectorPredicate()
98 return MI.findRegisterUseOperandIdx(ARM::VPR) != -1; in hasVPRUse()
203 assert((CurrentPredicates.size() || MI->getParent()->isLiveIn(ARM::VPR)) in CreateVPTBlock()
1036 if (RegMask.PhysReg == ARM::VPR) { in ValidateLiveOuts()
1248 if (!MO.isReg() || !MO.isUse() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
1691 MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR); in ConvertVPTBlocks()
H A DARMRegisterInfo.td203 // on the instruction they are used in and for VPR 32 was chosen such that it
205 def VPR : ARMReg<32, "vpr">;
400 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
458 // Scalar single and double precision floating point and VPR register class,
461 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
H A DARMInstrVFP.td326 let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV];
2523 // System level VPR/P0 -> GPR
2524 let Uses = [VPR] in
2594 // System level GPR -> VPR/P0
2595 let Defs = [VPR] in
2890 let Uses = [VPR] in {
2896 let Defs = [VPR] in {
H A DARMExpandPseudoInsts.cpp1388 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1399 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1479 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1573 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1757 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
H A DARMBaseInstrInfo.cpp881 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
990 } else if (DestReg == ARM::VPR) { in copyPhysReg()
996 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
H A DARMInstrMVE.td4483 // example when moving between rGPR and VPR.P0 as part of predicate vector
6602 let Defs = [VPR];
6714 let Defs = [VPR];
6761 let Uses = [VPR];
H A DARMInstrFormats.td226 // always either zero_reg or VPR, but needs to be modelled as an
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfoPOSIX_riscv64.h38 struct VPR { struct
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp107 for (VPRegionBlock *VPR : VPBlockUtils::blocksOnly<VPRegionBlock>(Iter)) { in sinkScalarOperands()
108 VPBasicBlock *EntryVPBB = VPR->getEntryBasicBlock(); in sinkScalarOperands()
109 if (!VPR->isReplicator() || EntryVPBB->getSuccessors().size() != 2) in sinkScalarOperands()
112 if (!VPBB || VPBB->getSingleSuccessor() != VPR->getExitingBasicBlock()) in sinkScalarOperands()
/freebsd-14.2/contrib/llvm-project/compiler-rt/include/profile/
H A DInstrProfData.inc473 getValueProfRecordNext(ValueProfRecord *VPR);
475 getValueProfRecordValueData(ValueProfRecord *VPR);
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ProfileData/
H A DInstrProfData.inc473 getValueProfRecordNext(ValueProfRecord *VPR);
475 getValueProfRecordValueData(ValueProfRecord *VPR);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6247 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6268 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6461 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6946 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6983 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6994 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6995 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dtegra124-venice2.dts65 * it after having set the VPR up
H A Dtegra124-jetson-tk1.dts74 * it after having set the VPR up
H A Dtegra124-apalis-v1.2.dtsi63 * it after having set the VPR up
H A Dtegra124-apalis.dtsi62 * it after having set the VPR up
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3717 if (Regs.back().second == ARM::VPR) in CreateRegList()
3723 if (Regs.back().second == ARM::VPR) in CreateRegList()
4563 if (Reg == ARM::VPR && in parseRegisterList()
/freebsd-14.2/contrib/ncurses/misc/
H A Dterminfo.src3546 # + in ECMA-48 cursor movement, VPR and HPR fail. Others work.
3626 # supports CHA, VPA, VPR, but no other ECMA-48 cursor movement such as HPA
3670 # supports CBT, CHA, VPA, CNL, CPL, VPR (no HPA, CHT, HPR)
7484 # CBT, CHT, HPR, CNL,CPL, VPR do not work
24543 # VPR Vert. Position Relative \E [ Pn e 1 FE - (R)
24670 # (R) Some ANSI.SYS versions accept VPR, but more commonly `ANSI' terminals
24671 # use CUD for this function and ignore VPR. ECMA calls it `Line Position