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Searched refs:VMOVDRR (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFixCortexA57AES1742098Pass.cpp163 case ARM::VMOVDRR: in isSafeAESInput()
H A DARMInstrVFP.td26 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
1180 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
1264 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1296 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1299 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
1302 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
1305 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
2773 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
H A DARMISelLowering.h116 VMOVDRR, // Two gprs to double. enumerator
H A DARMInstructionSelector.cpp256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
H A DARMScheduleM55.td458 def : InstRW<[M55WriteFloatE3], (instregex "VINSH$", "VMOVH$", "VMOVHR$", "VMOVSR$", "VMOVDRR$")>; …
H A DARM.td263 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
265 // True if VMOVSR will be favored over VMOVDRR.
H A DARMExpandPseudoInsts.cpp1324 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1489 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1720 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
H A DARMScheduleM85.td644 (instregex "VMOVDRR")>;
H A DARMScheduleSwift.td641 def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
H A DARMISelLowering.cpp1735 MAKE_CASE(ARMISD::VMOVDRR) in getTargetNodeName()
2234 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2251 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
5254 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
6028 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
6099 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
7151 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); in LowerConstantFP()
15045 if (InDouble.getOpcode() == ARMISD::VMOVDRR && Subtarget->hasFP64()) in PerformVMOVRRDCombine()
15600 if (MOV.getOpcode() == ARMISD::VMOVDRR) in PerformExtractEltCombine()
16821 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && in PerformSTORECombine()
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H A DARMScheduleA57.td807 def : InstRW<[A57Write_8cyc_1L_1I], (instregex "VMOVDRR")>;
H A DARMFastISel.cpp2044 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
H A DARMInstrNEON.td6658 // ARMvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
6659 def : Pat<(v2i32 (ARMvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
6661 def : Pat<(v2f32 (ARMvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
7497 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
7499 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
7502 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
H A DARMBaseInstrInfo.cpp5458 case ARM::VMOVDRR: in getRegSequenceLikeInputs()