Searched refs:VLSHR (Results 1 – 4 of 4) sorted by relevance
212 VLSHR, enumerator
2156 case AArch64ISD::VLSHR: { in computeKnownBitsForTargetNode()2456 MAKE_CASE(AArch64ISD::VLSHR) in getTargetNodeName()12758 (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR || in tryLowerToSLI()12765 (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR || in tryLowerToSLI()12774 bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR || in tryLowerToSLI()18275 if (Shr.getOpcode() != AArch64ISD::VLSHR) in performConcatVectorsCombine()18315 DAG.getNode(AArch64ISD::VLSHR, dl, BVT, Add, N0.getOperand(1)); in performConcatVectorsCombine()19657 : AArch64ISD::VLSHR; in tryCombineShiftImm()21061 N->getOpcode() == AArch64ISD::VLSHR); in performVectorShiftCombine()23970 case AArch64ISD::VLSHR: in PerformDAGCombine()[all …]
180 if (N.getOpcode() != AArch64ISD::VLSHR) in SelectRoundingVLShr()4332 N1->getOpcode() != AArch64ISD::VLSHR) in trySelectXAR()
723 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;