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Searched refs:VLD (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/sys/contrib/device-tree/Bindings/iommu/
H A Dmediatek,iommu.txt40 OVL0 RDMA0 WDMA0 MC PP VLD
50 in each larb. Take a example, There are many ports like MC, PP, VLD in the
H A Dmediatek,iommu.yaml50 OVL0 RDMA0 WDMA0 MC PP VLD
61 in each larb. Take a example, There are many ports like MC, PP, VLD in the
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td87 // Read the unwritten lanes of the VLD's destination registers.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td114 def : M4UnitL2I<(instregex "VLD")>;
H A DARMInstrInfo.td1339 // VLD/VST instructions and checking the alignment is not specified.
1350 // VLD/VST instructions and checking the alignment value.
1361 // VLD/VST instructions and checking the alignment value.
1372 // VLD/VST instructions and checking the alignment value.
1383 // for VLD/VST instructions and checking the alignment value.
1394 // encoding for VLD/VST instructions and checking the alignment value.
1404 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1425 // VLD-dup instruction and checking the alignment is not specified.
1435 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1457 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
[all …]
H A DARMScheduleM55.td446 def : InstRW<[M55WriteLSE3], (instregex "VLD")>;
H A DARMScheduleA57.td144 "VLD(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm",
145 "VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",
H A DARMISelLowering.cpp16372 SDNode *VLD = N->getOperand(0).getNode(); in CombineVLDDUP() local
16373 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) in CombineVLDDUP()
16377 unsigned IntNo = VLD->getConstantOperandVal(1); in CombineVLDDUP()
16393 unsigned VLDLaneNo = VLD->getConstantOperandVal(NumVecs + 3); in CombineVLDDUP()
16394 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
16412 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; in CombineVLDDUP()
16413 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); in CombineVLDDUP()
16414 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, in CombineVLDDUP()
16419 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
16435 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
H A DARMInstrNEON.td555 // Classes for VLD* pseudo-instructions with multi-register operands.
1001 // Classes for VLD*LN pseudo-instructions with multi-register operands.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td92 defm : VectorLoad<v256f64, i64, v256i1, "VGT", "VLD">;
93 defm : VectorLoad<v256i64, i64, v256i1, "VGT", "VLD">;
H A DVEInstrVec.td127 // Multiclass for VLD instructions
161 // Section 8.9.1 - VLD (Vector Load)
162 defm VLD : VLDm<"vld", 0x81, V64>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp165 Opcode = LoongArch::VLD; in loadRegFromStackSlot()
H A DLoongArchLSXInstrInfo.td1141 def VLD : LSX2RI12_Load<0x2c000000>;
1693 defm : LdPat<load, VLD, vt>;
2062 (VLD GPR:$rj, (to_valid_timm timm:$imm))>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFive7.td544 // VLD*R is LMUL aware