Home
last modified time | relevance | path

Searched refs:VGPR0 (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp92 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
93 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
94 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
95 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
H A DAMDGPUCallingConv.td33 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
47 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
80 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
113 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
196 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
208 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
H A DGCNNSAReassign.cpp148 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
150 for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) { in scavengeRegs()
H A DSIInsertWaitcnts.cpp102 unsigned VGPR0; member
729 assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL); in getRegInterval()
730 Result.first = Reg - Encoding.VGPR0; in getRegInterval()
2493 Encoding.VGPR0 = in runOnMachineFunction()
2494 TRI->getEncodingValue(AMDGPU::VGPR0) & AMDGPU::HWEncoding::REG_IDX_MASK; in runOnMachineFunction()
2495 Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1; in runOnMachineFunction()
H A DGCNHazardRecognizer.cpp1813 if (!TRI.isVGPR(MRI, AmtReg) || ((AmtReg - AMDGPU::VGPR0) & 7) != 7) in fixShift64HighRegBug()
1827 static_assert(AMDGPU::VGPR0 + 1 == AMDGPU::VGPR1); in fixShift64HighRegBug()
H A DSIRegisterInfo.cpp184 TmpVGPR = AMDGPU::VGPR0; in prepare()
443 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8; in isChainScratchRegister()
H A DAMDGPUCallLowering.cpp686 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
H A DSOPInstructions.td1068 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
H A DSIISelLowering.cpp2187 Register Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs()
2199 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2213 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2787 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4604 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4718 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()