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Searched refs:VGPR (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td136 (sequence "VGPR%u", 56, 63),
137 (sequence "VGPR%u", 72, 79),
138 (sequence "VGPR%u", 88, 95),
139 (sequence "VGPR%u", 104, 111),
140 (sequence "VGPR%u", 120, 127),
141 (sequence "VGPR%u", 136, 143),
142 (sequence "VGPR%u", 152, 159),
143 (sequence "VGPR%u", 168, 175),
144 (sequence "VGPR%u", 184, 191),
180 (sequence "VGPR%u", 8, 255)
[all …]
H A DSIRegisterInfo.td348 // VGPR registers
350 defm VGPR#Index :
617 // VGPR 32-bit registers
637 // VGPR 64-bit registers
640 // VGPR 96-bit registers
643 // VGPR 128-bit registers
646 // VGPR 160-bit registers
649 // VGPR 192-bit registers
652 // VGPR 224-bit registers
655 // VGPR 256-bit registers
[all …]
H A DSIRegisterInfo.h57 Register VGPR; member
61 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} in SpilledReg()
64 bool hasReg() { return VGPR != 0; } in hasReg()
98 static bool isChainScratchRegister(Register VGPR);
H A DAMDGPURegisterBanks.td13 def VGPRRegBank : RegisterBank<"VGPR",
H A DSIMachineFunctionInfo.cpp273 void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR, in allocateWWMSpill() argument
276 if (isEntryFunction() || WWMSpills.count(VGPR)) in allocateWWMSpill()
284 if (isChainFunction() && SIRegisterInfo::isChainScratchRegister(VGPR)) in allocateWWMSpill()
288 VGPR, MF.getFrameInfo().CreateSpillStackObject(Size, Alignment))); in allocateWWMSpill()
H A DSIFrameLowering.cpp108 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
279 Spill[I].VGPR) in saveToVGPRLane()
282 .addReg(Spill[I].VGPR, RegState::Undef); in saveToVGPRLane()
325 .addReg(Spill[I].VGPR) in restoreFromVGPRLane()
938 Register VGPR = Reg.first; in emitCSRSpillStores() local
941 VGPR, FI, FrameReg); in emitCSRSpillStores()
1041 Register VGPR = Reg.first; in emitCSRSpillRestores() local
1044 VGPR, FI, FrameReg); in emitCSRSpillRestores()
H A DSIInstrInfo.td95 SDTCisVT<2, i32>, // vindex(VGPR)
96 SDTCisVT<3, i32>, // voffset(VGPR)
113 SDTCisVT<2, i32>, // vindex(VGPR)
114 SDTCisVT<3, i32>, // voffset(VGPR)
131 SDTCisVT<2, i32>, // vindex(VGPR)
132 SDTCisVT<3, i32>, // voffset(VGPR)
159 SDTCisVT<2, i32>, // vindex(VGPR)
160 SDTCisVT<3, i32>, // voffset(VGPR)
225 SDTCisVT<4, i32>, // vindex(VGPR)
226 SDTCisVT<5, i32>, // voffset(VGPR)
[all …]
H A DSISchedule.td303 // Add 1 stall cycle for VGPR read.
336 // Add 1 stall cycle for VGPR read.
H A DAMDGPUGenRegisterBankInfo.def70 {0, 1, VGPRRegBank}, // VGPR begin
H A DSIPeepholeSDWA.cpp1176 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in legalizeScalarOperands() local
1178 TII->get(AMDGPU::V_MOV_B32_e32), VGPR); in legalizeScalarOperands()
1184 Op.ChangeToRegister(VGPR, false); in legalizeScalarOperands()
H A DSIRegisterInfo.cpp442 bool SIRegisterInfo::isChainScratchRegister(Register VGPR) { in isChainScratchRegister() argument
443 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8; in isChainScratchRegister()
1788 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR) in spillSGPR()
1791 .addReg(Spill.VGPR); in spillSGPR()
1898 .addReg(Spill.VGPR) in restoreSGPR()
H A DVOP1Instructions.td375 // Restrict src0 to be VGPR
733 // Restrict src0 to be VGPR
1330 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
1338 // Copy of v_mov_b32 for use with VGPR indexing mode. An implicit use of the
H A DAMDGPU.td257 …"Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of…
411 "Has VGPR mode register indexing"
846 "Has single-use VGPR hint instructions"
H A DSIMachineFunctionInfo.h675 void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size = 4,
H A DSIInstructions.td851 // These variants of V_INDIRECT_REG_READ/WRITE use VGPR indexing. By using these
853 // that switch the VGPR indexing mode. Spills to accvgprs could be effected by
956 // VGPR or AGPR spill instructions. In case of AGPR spilling a temp register
957 // needs to be used and an extra instruction to move between VGPR and AGPR.
3393 // Avoid pointlessly materializing a constant in VGPR.
H A DVOPInstructions.td444 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction.
H A DVOP3Instructions.td486 // blocking folding SGPR->VGPR copies later.
H A DFLATInstructions.td60 bits<1> has_sve = 0; // Scratch VGPR Enable
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td1323 [LLVMMatchType<0>, // src(VGPR)
1324 LLVMMatchType<0>, // cmp(VGPR)
1360 [LLVMMatchType<0>, // src(VGPR)
1361 LLVMMatchType<0>, // cmp(VGPR)
1419 [LLVMMatchType<0>, // src(VGPR)
1420 LLVMMatchType<0>, // cmp(VGPR)
1455 [LLVMMatchType<0>, // src(VGPR)
1456 LLVMMatchType<0>, // cmp(VGPR)
1723 [llvm_i32_ty, // src(VGPR)
2385 // be a VGPR function argument.
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