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Searched refs:VECTOR_SPLICE (Results 1 – 12 of 12) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h612 VECTOR_SPLICE, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp310 case ISD::VECTOR_SPLICE: return "vector_splice"; in getOperationName()
H A DLegalizeDAG.cpp3479 case ISD::VECTOR_SPLICE: { in ExpandNode()
5159 case ISD::VECTOR_SPLICE: { in PromoteNode()
5162 Tmp3 = DAG.getNode(ISD::VECTOR_SPLICE, dl, NVT, Tmp1, Tmp2, in PromoteNode()
H A DLegalizeIntegerTypes.cpp123 case ISD::VECTOR_SPLICE: in PromoteIntegerResult()
5535 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2)); in PromoteIntRes_VECTOR_SPLICE()
H A DLegalizeVectorTypes.cpp1042 case ISD::VECTOR_SPLICE: in SplitVectorResult()
H A DSelectionDAGBuilder.cpp12001 setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, in visitVectorSplice()
H A DSelectionDAG.cpp7136 case ISD::VECTOR_SPLICE: { in getNode()
H A DTargetLowering.cpp10814 assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!"); in expandVectorSplice()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp908 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp999 ISD::VECTOR_SPLICE, ISD::SIGN_EXTEND_INREG, in AArch64TargetLowering()
1313 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1487 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1634 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv2i1, MVT::nxv2i64); in AArch64TargetLowering()
1635 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32); in AArch64TargetLowering()
1636 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv8i1, MVT::nxv8i16); in AArch64TargetLowering()
1637 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv16i1, MVT::nxv16i8); in AArch64TargetLowering()
1941 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in addTypeForFixedLengthSVE()
6380 case ISD::VECTOR_SPLICE: in LowerOperation()
13567 SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ContainerVT, NewInVec, in LowerEXTRACT_SUBVECTOR()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td735 def vector_splice : SDNode<"ISD::VECTOR_SPLICE", SDTVecSlice, []>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp780 ISD::VECTOR_SPLICE, VT, in RISCVTargetLowering()
864 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in RISCVTargetLowering()
993 setOperationAction({ISD::VECTOR_REVERSE, ISD::VECTOR_SPLICE}, VT, Custom); in RISCVTargetLowering()
6416 case ISD::VECTOR_SPLICE: in LowerOperation()