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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 31) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1221 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1222 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1223 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
1224 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
1225 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
1226 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
1228 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
1229 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
1230 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
1242 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
[all …]
H A DARMISelLowering.cpp185 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
252 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
401 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
443 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
1026 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
10600 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
18605 N->getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE && in PerformMVETruncCombine()
18606 N->getOperand(1).getOpcode() == ISD::VECTOR_SHUFFLE) { in PerformMVETruncCombine()
18635 Op.getOpcode() == ISD::VECTOR_SHUFFLE || in PerformMVETruncCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h600 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1564 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1609 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
156 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW); in initializeHVXLowering()
157 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); in initializeHVXLowering()
158 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); in initializeHVXLowering()
159 setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); in initializeHVXLowering()
249 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
313 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
3533 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
3535 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in combineConcatVectorsBeforeLegal()
H A DHexagonISelLowering.cpp1645 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1759 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1760 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1761 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
3350 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp2823 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2833 if (V0.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
2835 if (V1.getOpcode() != ISD::VECTOR_SHUFFLE) in ppHvxShuffleOfShuffle()
H A DHexagonISelDAGToDAG.cpp926 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp255 case ISD::VECTOR_SHUFFLE: in getIdiomaticVectorType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp168 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
202 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
1474 case ISD::VECTOR_SHUFFLE: in LowerOperation()
2872 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp309 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DDAGCombiner.cpp2044 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
22326 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
22360 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
25880 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
25881 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
25898 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
25899 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
25954 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
25955 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
25956 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
[all …]
H A DSelectionDAG.cpp911 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
2193 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
2778 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2936 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
3140 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
4339 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
7134 case ISD::VECTOR_SHUFFLE: in getNode()
H A DLegalizeVectorTypes.cpp70 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
1039 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
4100 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
H A DLegalizeDAG.cpp3405 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
5146 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp490 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand); in NVPTXTargetLowering()
499 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2bf16, Expand); in NVPTXTargetLowering()
510 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i16, Expand); in NVPTXTargetLowering()
515 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in NVPTXTargetLowering()
2694 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp408 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
708 ISD::VECTOR_SHUFFLE, in SystemZTargetLowering()
5339 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
6191 case ISD::VECTOR_SHUFFLE: in LowerOperation()
6477 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
6950 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && in combineSTORE()
7677 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp816 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
817 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
893 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
1046 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in PPCTargetLowering()
1094 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in PPCTargetLowering()
1402 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
11661 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
15323 if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in combineVectorShuffle()
15324 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) { in combineVectorShuffle()
15637 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp254 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in LoongArchTargetLowering()
300 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in LoongArchTargetLowering()
421 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1901 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp343 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
459 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td322 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
H A DX86ISelLowering.cpp1110 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1117 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1583 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1690 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2432 setTargetDAGCombine({ISD::VECTOR_SHUFFLE, in X86TargetLowering()
5699 case ISD::VECTOR_SHUFFLE: { in getFauxShuffleMask()
8764 isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) { in LowerBUILD_VECTOR()
40635 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in isAddSubOrSubAdd()
40688 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in combineShuffleToFMAddSub()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1703 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
1940 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForFixedLengthSVE()
6218 case ISD::VECTOR_SHUFFLE: in LowerOperation()
13351 SDValue VECTOR_SHUFFLE = in LowerBUILD_VECTOR() local
13353 return VECTOR_SHUFFLE; in LowerBUILD_VECTOR()
16951 BV.getOpcode() != ISD::VECTOR_SHUFFLE) in performBuildShuffleExtendCombine()
16966 if (BV.getOpcode() == ISD::VECTOR_SHUFFLE && in performBuildShuffleExtendCombine()
19307 } else if (B.getOpcode() == ISD::VECTOR_SHUFFLE) { in isLoadOrMultipleLoads()
19321 if (B.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE || in isLoadOrMultipleLoads()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp468 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
488 ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, ISD::SETCC, in AMDGPUTargetLowering()

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