Searched refs:VECTOR_INTERLEAVE (Results 1 – 7 of 7) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 586 VECTOR_INTERLEAVE, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 307 case ISD::VECTOR_INTERLEAVE: return "vector_interleave"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 1048 case ISD::VECTOR_INTERLEAVE: in SplitVectorResult()
2937 SDValue Res[] = {DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, in SplitVecRes_VECTOR_INTERLEAVE()
2939 DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, in SplitVecRes_VECTOR_INTERLEAVE()
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| H A D | LegalizeIntegerTypes.cpp | 125 case ISD::VECTOR_INTERLEAVE: in PromoteIntegerResult()
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| H A D | SelectionDAGBuilder.cpp | 11964 SDValue Res = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, in visitVectorInterleave()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 772 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in RISCVTargetLowering()
861 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in RISCVTargetLowering()
991 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in RISCVTargetLowering()
6410 case ISD::VECTOR_INTERLEAVE: in LowerOperation()
9783 SDValue ResLo = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, in lowerVECTOR_INTERLEAVE()
9785 SDValue ResHi = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, in lowerVECTOR_INTERLEAVE()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1290 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in AArch64TargetLowering()
1337 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in AArch64TargetLowering()
1489 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in AArch64TargetLowering()
6384 case ISD::VECTOR_INTERLEAVE: in LowerOperation()
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