| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1359 VECREDUCE_OR, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 502 case ISD::VECREDUCE_OR: return "vecreduce_or"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 463 case ISD::VECREDUCE_OR: in LegalizeOp()
1117 case ISD::VECREDUCE_OR: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 259 case ISD::VECREDUCE_OR: in PromoteIntegerResult()
1858 case ISD::VECREDUCE_OR: in PromoteIntegerOperand()
2405 case ISD::VECREDUCE_OR: in getExtendForIntVecReduction()
2458 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2459 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_OR, InVT) && in PromoteIntOp_VECREDUCE()
2756 case ISD::VECREDUCE_OR: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 728 case ISD::VECREDUCE_OR: in ScalarizeVectorOperand()
3057 case ISD::VECREDUCE_OR: in SplitVectorOperand()
6094 case ISD::VECREDUCE_OR: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1215 case ISD::VECREDUCE_OR: in LegalizeOp()
4229 case ISD::VECREDUCE_OR: in ExpandNode()
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| H A D | SelectionDAG.cpp | 446 case ISD::VECREDUCE_OR: in getVecReduceBaseOpcode()
5870 return getNode(ISD::VECREDUCE_OR, DL, VT, N1); in getNode()
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| H A D | DAGCombiner.cpp | 2064 case ISD::VECREDUCE_OR: in visit()
7960 if (SDValue SD = reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, SDLoc(N), in visitOR()
26343 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
26358 if ((Opcode == ISD::VECREDUCE_OR && in visitVECREDUCE()
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| H A D | SelectionDAGBuilder.cpp | 10222 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); in visitVectorReduce()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 900 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1024 setTargetDAGCombine(ISD::VECREDUCE_OR); in AArch64TargetLowering()
1203 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1330 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1390 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1932 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addTypeForFixedLengthSVE()
6302 case ISD::VECREDUCE_OR: in LowerOperation()
14102 case ISD::VECREDUCE_OR: in getVectorBitwiseReduce()
14220 case ISD::VECREDUCE_OR: in LowerVECREDUCE()
14251 case ISD::VECREDUCE_OR: in LowerVECREDUCE()
23847 case ISD::VECREDUCE_OR: in PerformDAGCombine()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 694 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
740 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1119 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
6369 case ISD::VECREDUCE_OR: in LowerOperation()
9072 case ISD::VECREDUCE_OR: in getRVVReductionOp()
9096 Op.getOpcode() == ISD::VECREDUCE_OR || in lowerVectorMaskVecReduction()
9137 case ISD::VECREDUCE_OR: in lowerVectorMaskVecReduction()
12023 case ISD::VECREDUCE_OR: in ReplaceNodeResults()
12072 return ISD::VECREDUCE_OR; in getVecReduceOpcode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 351 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 301 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addMVEVectorTypes()
10286 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break; in LowerVecReduce()
10645 case ISD::VECREDUCE_OR: in LowerOperation()
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