| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1358 VECREDUCE_AND, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 501 case ISD::VECREDUCE_AND: return "vecreduce_and"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 462 case ISD::VECREDUCE_AND: in LegalizeOp()
1116 case ISD::VECREDUCE_AND: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 258 case ISD::VECREDUCE_AND: in PromoteIntegerResult()
1857 case ISD::VECREDUCE_AND: in PromoteIntegerOperand()
2404 case ISD::VECREDUCE_AND: in getExtendForIntVecReduction()
2477 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2478 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_AND, InVT) && in PromoteIntOp_VECREDUCE()
2755 case ISD::VECREDUCE_AND: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 727 case ISD::VECREDUCE_AND: in ScalarizeVectorOperand()
3056 case ISD::VECREDUCE_AND: in SplitVectorOperand()
6093 case ISD::VECREDUCE_AND: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1214 case ISD::VECREDUCE_AND: in LegalizeOp()
4228 case ISD::VECREDUCE_AND: in ExpandNode()
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| H A D | DAGCombiner.cpp | 2063 case ISD::VECREDUCE_AND: in visit()
7032 if (SDValue SD = reassociateReduction(ISD::VECREDUCE_AND, ISD::AND, SDLoc(N), in visitAND()
26343 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
26344 unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND in visitVECREDUCE()
26360 (Opcode == ISD::VECREDUCE_AND && in visitVECREDUCE()
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| H A D | SelectionDAG.cpp | 443 case ISD::VECREDUCE_AND: in getVecReduceBaseOpcode()
5875 return getNode(ISD::VECREDUCE_AND, DL, VT, N1); in getNode()
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| H A D | SelectionDAGBuilder.cpp | 10219 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); in visitVectorReduce()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 900 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1023 setTargetDAGCombine(ISD::VECREDUCE_AND); in AArch64TargetLowering()
1202 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1329 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1389 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1926 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addTypeForFixedLengthSVE()
6301 case ISD::VECREDUCE_AND: in LowerOperation()
14099 case ISD::VECREDUCE_AND: in getVectorBitwiseReduce()
14218 case ISD::VECREDUCE_AND: in LowerVECREDUCE()
14250 case ISD::VECREDUCE_AND: in LowerVECREDUCE()
23846 case ISD::VECREDUCE_AND: in PerformDAGCombine()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 694 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
740 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1119 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
6368 case ISD::VECREDUCE_AND: in LowerOperation()
9069 case ISD::VECREDUCE_AND: in getRVVReductionOp()
9095 assert((Op.getOpcode() == ISD::VECREDUCE_AND || in lowerVectorMaskVecReduction()
9127 case ISD::VECREDUCE_AND: in lowerVectorMaskVecReduction()
12022 case ISD::VECREDUCE_AND: in ReplaceNodeResults()
12070 return ISD::VECREDUCE_AND; in getVecReduceOpcode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 350 ISD::VECREDUCE_ADD, ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, in initVPUActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 300 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addMVEVectorTypes()
10285 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break; in LowerVecReduce()
10644 case ISD::VECREDUCE_AND: in LowerOperation()
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