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Searched refs:VALU (Results 1 – 22 of 22) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp60 enum DelayType { VALU, TRANS, SALU, OTHER }; enumerator
66 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
67 return VALU; in getDelayType()
117 case VALU: in DelayInfo()
160 VALUNum += (Type == VALU); in advance()
172 TRANSNumVALU += (Type == VALU); in advance()
H A DSIInstrFormats.td18 field bit VALU = 0;
27 // VALU instruction formats.
169 let TSFlags{1} = VALU;
261 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
277 let VALU = 1;
546 let VALU = 1;
H A DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
36 // Other quarter rate VALU instructions
74 // FIXME: Should there be a class for instructions which are VALU
75 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
120 def HWTransVALU : ProcResource<1> { // Transcendental VALU
H A DAMDGPUIGroupLP.cpp69 VALU = 1u << 1, enumerator
79 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
1215 SchedGroupMask::VALU, 2, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1251 SchedGroupMask::VALU, 4, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1308 SchedGroupMask::VALU, 4, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1322 SchedGroupMask::VALU, 4, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1443 else if (((SGMask & SchedGroupMask::VALU) != SchedGroupMask::NONE) && in canAddMI()
1666 InvertedMask &= ~SchedGroupMask::VALU & ~SchedGroupMask::SALU & in invertSchedBarrierMask()
1669 else if ((InvertedMask & SchedGroupMask::VALU) == SchedGroupMask::NONE || in invertSchedBarrierMask()
H A DGCNHazardRecognizer.cpp884 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { in checkVALUHazards() argument
887 if (ST.hasTransForwardingHazard() && !SIInstrInfo::isTRANS(*VALU)) { in checkVALUHazards()
890 auto IsTransDefFn = [this, VALU](const MachineInstr &MI) { in checkVALUHazards()
897 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
914 auto IsShift16BitDefFn = [this, VALU](const MachineInstr &MI) { in checkVALUHazards()
933 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
962 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
976 if (VALU->readsRegister(AMDGPU::VCC, TRI)) { in checkVALUHazards()
984 switch (VALU->getOpcode()) { in checkVALUHazards()
987 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
[all …]
H A DGCNHazardRecognizer.h89 int checkVALUHazards(MachineInstr *VALU);
H A DVOPInstructions.td69 let VALU = 1;
150 let VALU = 1;
186 let VALU = 1;
608 let VALU = 1;
629 let VALU = 1;
660 let VALU = 1;
819 let VALU = 1;
859 let VALU = 1;
899 let VALU = 1;
989 let VALU = 1;
H A DVOPDInstructions.td78 let VALU = 1;
H A DSIDefines.h56 VALU = 1 << 1, enumerator
H A DSIInstrInfo.h417 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
421 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
H A DFLATInstructions.td104 let VALU = ps.VALU;
167 let VALU = ps.VALU;
303 let VALU = 1;
490 let VALU = 1;
H A DVOP1Instructions.td56 let VALU = 1;
67 let VALU = 1;
256 let VALU = 1;
H A DBUFInstructions.td350 let VALU = ps.VALU;
510 let VALU = isLds;
676 let VALU = 1;
2368 let VALU = ps.VALU;
H A DSIInstructions.td801 let VALU = 1;
859 let VALU = 1;
879 let VALU = 1;
934 let SGPRSpill = 1, VALU = 1, isConvergent = 1 in {
954 } // End SGPRSpill = 1, VALU = 1, isConvergent = 1
2603 // will be moved to the VALU.
2845 // Handle the VALU case.
H A DSIInstrInfo.td1125 // 32-bit VALU immediate operand that uses the constant bus.
1128 // 32-bit VALU immediate operand with a 16-bit value that uses the
H A DVOP2Instructions.td77 let VALU = 1;
88 let VALU = 1;
H A DVOPCInstructions.td151 let VALU = 1;
163 let VALU = 1;
H A DAMDGPU.td94 "Have VALU add/sub instructions without carry out"
H A DVOP3Instructions.td455 // Only use VALU ops when the result is divergent.
H A DSOPInstructions.td763 // Use added complexity so these patterns are preferred to the VALU patterns.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td456 let PPC970_Unit = 5 in { // VALU Operations.
858 } // VALU Operations.
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td279 // MASK = 0x0000 0002: VALU instructions may be scheduled across SCHED_BARRIER.