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Searched refs:UndefReg (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp53 std::vector<Register> UndefReg; member in __anon6eb6162d0111::RegSeqInfo
61 UndefReg.push_back(Chan); in RegSeqInfo()
161 if (CurrentUndexIdx >= Untouched->UndefReg.size()) in tryMergeVector()
164 It.second, Untouched->UndefReg[CurrentUndexIdx++])); in tryMergeVector()
191 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg; in RebuildVector()
229 RSI->UndefReg = UpdatedUndef; in RebuildVector()
295 unsigned NeededUndefs = 4 - RSI.UndefReg.size(); in tryMergeUsingFreeSlot()
310 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
H A DSIOptimizeVGPRLiveRange.cpp508 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() local
515 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeLiveRange()
560 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange() local
577 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeWaterfallLiveRange()
H A DSILowerI1Copies.cpp425 Register UndefReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in insertUndefLaneMask() local
427 UndefReg); in insertUndefLaneMask()
428 return UndefReg; in insertUndefLaneMask()
H A DAMDGPUInstructionSelector.cpp2423 Register UndefReg = MRI->createVirtualRegister(SrcRC); in selectG_SZA_EXT() local
2424 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2428 .addReg(UndefReg) in selectG_SZA_EXT()
2506 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2509 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2513 .addReg(UndefReg) in selectG_SZA_EXT()
H A DSIISelLowering.cpp14763 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
14766 UndefReg, Src0, SDValue()); in PostISelFolding()
14780 Src0 = UndefReg; in PostISelFolding()
14781 Src1 = UndefReg; in PostISelFolding()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallFrameOptimization.cpp534 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
536 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg); in adjustCallSequence()
538 .addReg(UndefReg) in adjustCallSequence()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp368 Register UndefReg; in matchCombineShuffleVector() local
372 if (!UndefReg) { in matchCombineShuffleVector()
374 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
376 Ops.push_back(UndefReg); in matchCombineShuffleVector()
2956 Register UndefReg; in applyCombineInsertVecElts() local
2958 if (UndefReg) in applyCombineInsertVecElts()
2959 return UndefReg; in applyCombineInsertVecElts()
2961 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2962 return UndefReg; in applyCombineInsertVecElts()
H A DLegalizerHelper.cpp1873 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
1875 Unmerges.push_back(UndefReg); in widenScalarMergeValues()