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Searched refs:UREM (Results 1 – 25 of 44) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h108 case ISD::UREM:
H A DLanaiISelLowering.cpp111 setOperationAction(ISD::UREM, MVT::i32, Expand); in LanaiTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1352 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1356 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1360 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1364 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1369 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1373 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1377 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1381 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2093 case ISD::UREM: in maybeLoweredToCall()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h245 UREM, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp338 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
400 { ISD::UREM, MVT::v16i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
441 { ISD::UREM, MVT::v8i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
513 { ISD::UREM, MVT::v4i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
533 { ISD::UREM, MVT::v32i16, { 8 } }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
556 { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
574 { ISD::UREM, MVT::v16i16, { 8 } }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
579 { ISD::UREM, MVT::v8i32, { 19 } }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
629 { ISD::UREM, MVT::v8i16, { 8 } }, // pmulhuw+mul+sub sequence in getArithmeticInstrCost()
634 { ISD::UREM, MVT::v4i32, { 20 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1927 case ISD::UREM: in selectDivRem()
1944 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2049 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
2050 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
H A DMipsSEISelLowering.cpp235 setOperationAction(ISD::UREM, MVT::i32, Legal); in MipsSETargetLowering()
282 setOperationAction(ISD::UREM, MVT::i64, Legal); in MipsSETargetLowering()
340 setOperationAction(ISD::UREM, Ty, Legal); in addMSAIntType()
2051 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp348 case ISD::UREM: in LegalizeOp()
1136 case ISD::UREM: in Expand()
1836 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
H A DSelectionDAGBuilder.h545 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
H A DSelectionDAGDumper.cpp250 case ISD::UREM: return "urem"; in getOperationName()
H A DFastISel.cpp498 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && in selectBinaryOp()
1784 return selectBinaryOp(I, ISD::UREM); in selectOperator()
H A DTargetLowering.cpp4817 if (N0.getOpcode() == ISD::UREM && N1C->isZero() && in SimplifySetCC()
5290 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && in SimplifySetCC()
5295 if (N0.getOpcode() == ISD::UREM) { in SimplifySetCC()
7622 (Opcode == ISD::UREM || Opcode == ISD::UDIV || Opcode == ISD::UDIVREM) && in expandDIVREMByConstant()
7724 DAG.getNode(ISD::UREM, dl, HiLoVT, Sum, in expandDIVREMByConstant()
7728 if (Opcode != ISD::UREM) { in expandDIVREMByConstant()
7888 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
7903 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
7967 SDValue ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Op1, BitWidthC); in expandROT()
H A DLegalizeDAG.cpp3696 case ISD::UREM: in ExpandNode()
4804 case ISD::UREM: in ConvertNodeToLibcall()
5053 case ISD::UREM: in PromoteNode()
5079 case ISD::UREM: in PromoteNode()
H A DSelectionDAG.cpp3813 case ISD::UREM: { in computeKnownBits()
5934 case ISD::UREM: in FoldValue()
6031 case ISD::UREM: { in isUndef()
6642 case ISD::UREM: in getNode()
6993 case ISD::UREM: in getNode()
7015 case ISD::UREM: in getNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp134 setOperationAction(ISD::UREM, MVT::i8, Promote); in MSP430TargetLowering()
140 setOperationAction(ISD::UREM, MVT::i16, LibCall); in MSP430TargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp531 ISD::UMIN, ISD::UMULO, ISD::UMUL_LOHI, ISD::UREM, in NVPTXTargetLowering()
693 setI16x2OperationAction(ISD::UREM, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
726 ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, in NVPTXTargetLowering()
2731 case ISD::UREM: in LowerOperation()
5322 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
5671 case ISD::UREM: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp989 case ISD::UREM: in canOpTrap()
1862 case URem: return ISD::UREM; in InstructionOpcodeToISD()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def204 HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp153 setOperationAction(ISD::UREM, MVT::i8, Expand); in AVRTargetLowering()
154 setOperationAction(ISD::UREM, MVT::i16, Expand); in AVRTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4616 case ISD::UREM: in selectRem()
5113 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
5114 return selectRem(I, ISD::UREM); in fastSelectInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp59 setOperationAction(ISD::UREM, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp258 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
304 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
2785 return DAG.getNode(ISD::UREM, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1675 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1682 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1580 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1627 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp328 setOperationAction(ISD::UREM, MVT::i32, Legal); in PPCTargetLowering()
330 setOperationAction(ISD::UREM, MVT::i64, Legal); in PPCTargetLowering()
333 setOperationAction(ISD::UREM, MVT::i32, Expand); in PPCTargetLowering()
335 setOperationAction(ISD::UREM, MVT::i64, Expand); in PPCTargetLowering()
841 setOperationAction(ISD::UREM, VT, Expand); in PPCTargetLowering()
962 setOperationAction(ISD::UREM, MVT::v2i64, Legal); in PPCTargetLowering()
964 setOperationAction(ISD::UREM, MVT::v4i32, Legal); in PPCTargetLowering()
966 setOperationAction(ISD::UREM, MVT::v1i128, Legal); in PPCTargetLowering()

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