| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsTargetTransformInfo.cpp | 15 return TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, in hasDivRemOp()
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| H A D | MipsSEISelLowering.cpp | 191 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
198 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
231 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
278 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
452 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, in LowerOperation()
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| H A D | MipsISelLowering.cpp | 491 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, in MipsTargetLowering()
1161 case ISD::UDIVREM: in PerformDAGCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 256 UDIVREM, enumerator
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| H A D | SelectionDAG.h | 2370 case ISD::UDIVREM:
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| H A D | BasicTTIImpl.h | 925 if (TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 161 setOperationAction(ISD::UDIVREM, MVT::i8, Custom); in AVRTargetLowering()
162 setOperationAction(ISD::UDIVREM, MVT::i16, Custom); in AVRTargetLowering()
163 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AVRTargetLowering()
557 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
1017 case ISD::UDIVREM: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 96 UDIVREM, enumerator
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| H A D | SystemZOperators.td | 288 def z_udivrem : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>;
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| H A D | SystemZISelLowering.cpp | 183 setOperationAction(ISD::UDIVREM, VT, Custom); in SystemZTargetLowering()
246 setOperationAction(ISD::UDIVREM, MVT::i128, Expand); in SystemZTargetLowering()
4184 lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM, in lowerUDIVREM()
6135 case ISD::UDIVREM: in LowerOperation()
6334 OPCODE(UDIVREM); in getTargetNodeName()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 133 setOperationAction(ISD::UDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
139 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 254 case ISD::UDIVREM: return "udivrem"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 4887 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_UDIV()
4888 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_UDIV()
4930 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_UREM()
4931 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_UREM()
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| H A D | LegalizeVectorOps.cpp | 350 case ISD::UDIVREM: in LegalizeOp()
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| H A D | LegalizeDAG.cpp | 3704 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
4823 case ISD::UDIVREM: in ConvertNodeToLibcall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 101 setOperationAction(ISD::UDIVREM, VT, Expand); in BPFTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 416 setOperationAction({ISD::SDIVREM, ISD::UDIVREM}, VT, Custom); in AMDGPUTargetLowering()
465 ISD::UMUL_LOHI, ISD::SDIVREM, ISD::UDIVREM, in AMDGPUTargetLowering()
1338 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
2004 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
2292 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
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| H A D | R600ISelLowering.cpp | 613 case ISD::UDIVREM: { in ReplaceNodeResults()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 109 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 60 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in CSKYTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1678 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1685 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1581 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1627 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 206 setOperationAction(ISD::UDIVREM, VT, Expand); in addTypeForNEON()
287 setOperationAction(ISD::UDIVREM, VT, Expand); in addMVEVectorTypes()
1289 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in ARMTargetLowering()
1291 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in ARMTargetLowering()
1294 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in ARMTargetLowering()
10662 case ISD::UDIVREM: return LowerDivRem(Op, DAG); in LowerOperation()
10731 case ISD::UDIVREM: in ReplaceNodeResults()
20656 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemLibcall()
20674 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemArgList()
20701 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
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| H A D | ARMTargetTransformInfo.cpp | 2095 case ISD::UDIVREM: in maybeLoweredToCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 145 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
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