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Searched refs:TrueReg (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp789 Register TrueReg = in simplifyCode() local
791 if (!TrueReg.isVirtual()) in simplifyCode()
793 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
856 Register TrueReg = in simplifyCode() local
858 if (!TrueReg.isVirtual()) in simplifyCode()
860 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
1205 Register TrueReg = in simplifyCode() local
1207 if (!TrueReg.isVirtual() || !MRI->hasOneNonDBGUse(TrueReg)) in simplifyCode()
1210 MachineInstr *SrcMI = MRI->getVRegDef(TrueReg); in simplifyCode()
H A DPPCInstrInfo.cpp1614 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1615 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3197 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3204 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3206 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3208 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3220 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3356 Register TrueReg = TRI->lookThruCopyLike(Reg, MRI); in getForwardingDefMI() local
3357 if (TrueReg.isVirtual()) { in getForwardingDefMI()
4544 Register TrueReg = CompareUseMI.getOperand(1).getReg(); in simplifyToLI() local
[all …]
H A DPPCInstrInfo.h438 ArrayRef<MachineOperand> Cond, Register TrueReg,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp787 auto TrueReg = MIB.getReg(2); in selectSelect() local
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
794 .addUse(TrueReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2355 MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
2358 const TargetRegisterClass *TrueClass = MRI.getRegClass(TrueReg.getReg()); in optimizeSelect()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp918 Register TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
919 if (TrueReg == 0) in selectSelect()
927 std::swap(TrueReg, FalseReg); in selectSelect()
965 .addReg(TrueReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp491 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
497 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
531 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); in LowerFPToInt()
535 .addReg(TrueReg) in LowerFPToInt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp552 Register DstReg, Register TrueReg, in canInsertSelect() argument
565 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
588 Register TrueReg, in insertSelect() argument
608 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
610 TrueReg = TReg; in insertSelect()
622 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h255 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DSystemZISelLowering.cpp8113 Register TrueReg = MI->getOperand(1).getReg(); in createPHIsForSelects() local
8120 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
8122 if (RegRewriteTable.contains(TrueReg)) in createPHIsForSelects()
8123 TrueReg = RegRewriteTable[TrueReg].first; in createPHIsForSelects()
8130 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
8134 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h367 Register TrueReg, Register FalseReg, int &CondCycles,
373 Register TrueReg, Register FalseReg) const override;
378 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1247 .addReg(TrueReg) in insertVectorSelect()
1262 .addReg(TrueReg) in insertVectorSelect()
1276 .addReg(TrueReg) in insertVectorSelect()
1290 .addReg(TrueReg) in insertVectorSelect()
1302 .addReg(TrueReg) in insertVectorSelect()
1322 .addReg(TrueReg) in insertVectorSelect()
1340 .addReg(TrueReg) in insertVectorSelect()
3219 std::swap(TrueReg, FalseReg); in insertSelect()
3230 .addReg(TrueReg) in insertSelect()
3236 .addReg(TrueReg); in insertSelect()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h910 Register TrueReg, Register FalseReg, in canInsertSelect() argument
934 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h388 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DX86InstrInfo.cpp3995 Register DstReg, Register TrueReg, in canInsertSelect() argument
4010 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
4033 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
4043 .addReg(TrueReg) in insertSelect()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h257 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DAArch64InstrInfo.cpp700 Register DstReg, Register TrueReg, in canInsertSelect() argument
707 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
727 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
751 Register TrueReg, Register FalseReg) const { in insertSelect() argument
854 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
859 TrueReg = FalseReg; in insertSelect()
873 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
878 .addReg(TrueReg) in insertSelect()