| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 120 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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| H A D | LanaiInstrInfo.cpp | 439 unsigned &TrueOp, unsigned &FalseOp, in analyzeSelect() argument
447 TrueOp = 1; in analyzeSelect()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1953 auto *TrueOp = dyn_cast<ConstantSDNode>(Node->getOperand(0)); in expandSelectBoolean() local
1955 if (!TrueOp || !FalseOp) in expandSelectBoolean()
1959 if (TrueOp->getSExtValue() != 1 && TrueOp->getSExtValue() != -1) in expandSelectBoolean()
1984 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean()
1991 if (TrueOp->getSExtValue() == 1) { in expandSelectBoolean()
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| H A D | SystemZISelLowering.cpp | 3456 SDValue TrueOp = Op.getOperand(2); in lowerSELECT_CC() local
3471 if (isAbsolute(C.Op0, TrueOp, FalseOp)) in lowerSELECT_CC()
3472 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT); in lowerSELECT_CC()
3473 if (isAbsolute(C.Op0, FalseOp, TrueOp)) in lowerSELECT_CC()
3478 SDValue Ops[] = {TrueOp, FalseOp, in lowerSELECT_CC()
6610 auto *TrueOp = dyn_cast<ConstantSDNode>(N0.getOperand(0)); in combineZERO_EXTEND() local
6612 if (TrueOp && FalseOp) { in combineZERO_EXTEND()
6614 SDValue Ops[] = { DAG.getConstant(TrueOp->getZExtValue(), DL, VT), in combineZERO_EXTEND()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 133 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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| H A D | RISCVInstrInfo.cpp | 1403 unsigned &TrueOp, unsigned &FalseOp, in analyzeSelect() argument
1414 TrueOp = 5; in analyzeSelect()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 691 unsigned TrueOp = 0; in optimizeSelect() local
695 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable)) in optimizeSelect()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 304 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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| H A D | ARMBaseInstrInfo.cpp | 2320 unsigned &TrueOp, unsigned &FalseOp, in analyzeSelect() argument
2330 TrueOp = 1; in analyzeSelect()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 958 unsigned &TrueOp, unsigned &FalseOp, in analyzeSelect() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46127 SDValue TrueOp = N->getOperand(1); in combineCMov() local
46132 if (TrueOp == FalseOp) in combineCMov()
46133 return TrueOp; in combineCMov()
46158 std::swap(TrueOp, FalseOp); in combineCMov()
46258 std::swap(TrueOp, FalseOp); in combineCMov()
46319 std::swap(FalseOp, TrueOp); in combineCMov()
46340 SDValue Add = TrueOp; in combineCMov()
54406 TrueOp = DAG.getNode(ISD::ADD, DL, VT, X, TrueOp); in pushAddIntoCmovOfConsts()
54414 TrueOp = DAG.getNode(ISD::ADD, DL, VT, OtherOp, TrueOp); in pushAddIntoCmovOfConsts()
54500 SDValue TrueOp = N1.getOperand(1); in combineSubABS() local
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