| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 75 case TargetOpcode::G_LOAD: in classof()
76 case TargetOpcode::G_STORE: in classof()
176 case TargetOpcode::G_LOAD: in classof()
365 case TargetOpcode::G_UADDO: in classof()
366 case TargetOpcode::G_SADDO: in classof()
367 case TargetOpcode::G_USUBO: in classof()
368 case TargetOpcode::G_SSUBO: in classof()
369 case TargetOpcode::G_UADDE: in classof()
370 case TargetOpcode::G_SADDE: in classof()
371 case TargetOpcode::G_USUBE: in classof()
[all …]
|
| H A D | MIPatternMatch.h | 450 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>
570 inline UnaryOp_match<SrcTy, TargetOpcode::G_ANYEXT>
577 return UnaryOp_match<SrcTy, TargetOpcode::G_SEXT>(Src);
582 return UnaryOp_match<SrcTy, TargetOpcode::G_ZEXT>(Src);
596 inline UnaryOp_match<SrcTy, TargetOpcode::G_BITCAST>
602 inline UnaryOp_match<SrcTy, TargetOpcode::G_PTRTOINT>
608 inline UnaryOp_match<SrcTy, TargetOpcode::G_INTTOPTR>
614 inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTRUNC>
621 return UnaryOp_match<SrcTy, TargetOpcode::G_FABS>(Src);
626 return UnaryOp_match<SrcTy, TargetOpcode::G_FNEG>(Src);
[all …]
|
| H A D | Utils.h | 55 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
56 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
57 case TargetOpcode::G_VECREDUCE_FADD: \
58 case TargetOpcode::G_VECREDUCE_FMUL: \
59 case TargetOpcode::G_VECREDUCE_FMAX: \
60 case TargetOpcode::G_VECREDUCE_FMIN: \
61 case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
62 case TargetOpcode::G_VECREDUCE_FMINIMUM: \
63 case TargetOpcode::G_VECREDUCE_ADD: \
71 case TargetOpcode::G_VECREDUCE_UMIN:
[all …]
|
| H A D | LegalizationArtifactCombiner.h | 42 case TargetOpcode::G_TRUNC: in isArtifactCast()
43 case TargetOpcode::G_SEXT: in isArtifactCast()
44 case TargetOpcode::G_ZEXT: in isArtifactCast()
45 case TargetOpcode::G_ANYEXT: in isArtifactCast()
367 assert(Opcode == TargetOpcode::G_ANYEXT || Opcode == TargetOpcode::G_ZEXT || in tryFoldImplicitDef()
1310 case TargetOpcode::G_ZEXT: in tryCombineInstruction()
1313 case TargetOpcode::G_SEXT: in tryCombineInstruction()
1338 case TargetOpcode::G_TRUNC: in tryCombineInstruction()
1392 case TargetOpcode::COPY: in getArtifactSrcReg()
1394 case TargetOpcode::G_ZEXT: in getArtifactSrcReg()
[all …]
|
| H A D | MachineIRBuilder.h | 622 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
630 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
638 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
646 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
703 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src}); in buildBitcast()
1200 return buildInstr(TargetOpcode::G_IS_FPCLASS, {Res}, in buildIsFPClass()
1539 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src}); in buildFreeze()
1725 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0}); in buildCTPOP()
1730 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0}); in buildCTLZ()
1740 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0}); in buildCTTZ()
[all …]
|
| H A D | IRTranslator.h | 446 return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder); in translateAdd()
449 return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder); in translateSub()
458 return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder); in translateOr()
483 return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder); in translateTrunc()
489 return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder); in translateFPExt()
492 return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder); in translateFPToUI()
495 return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder); in translateFPToSI()
498 return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder); in translateUIToFP()
501 return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder); in translateSIToFP()
506 return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder); in translateSExt()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVRegisterBankInfo.cpp | 132 case TargetOpcode::G_FADD: in isPreISelGenericFloatingPointOpcode()
133 case TargetOpcode::G_FSUB: in isPreISelGenericFloatingPointOpcode()
134 case TargetOpcode::G_FMUL: in isPreISelGenericFloatingPointOpcode()
135 case TargetOpcode::G_FMA: in isPreISelGenericFloatingPointOpcode()
136 case TargetOpcode::G_FDIV: in isPreISelGenericFloatingPointOpcode()
143 case TargetOpcode::G_FNEG: in isPreISelGenericFloatingPointOpcode()
244 case TargetOpcode::G_ADD: in getInstrMapping()
245 case TargetOpcode::G_SUB: in getInstrMapping()
246 case TargetOpcode::G_SHL: in getInstrMapping()
249 case TargetOpcode::G_AND: in getInstrMapping()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.cpp | 93 case TargetOpcode::G_ADD: in getInstrMapping()
94 case TargetOpcode::G_SUB: in getInstrMapping()
96 case TargetOpcode::G_AND: in getInstrMapping()
97 case TargetOpcode::G_OR: in getInstrMapping()
98 case TargetOpcode::G_XOR: in getInstrMapping()
100 case TargetOpcode::G_SEXT: in getInstrMapping()
101 case TargetOpcode::G_ZEXT: in getInstrMapping()
117 case TargetOpcode::G_FADD: in getInstrMapping()
118 case TargetOpcode::G_FSUB: in getInstrMapping()
119 case TargetOpcode::G_FMUL: in getInstrMapping()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 300 case TargetOpcode::G_OR: { in getInstrAlternativeMappings()
400 case TargetOpcode::G_OR: in applyMappingImpl()
402 case TargetOpcode::G_LOAD: in applyMappingImpl()
420 case TargetOpcode::G_FMA: in isPreISelGenericFloatingPointOpcode()
673 case TargetOpcode::G_ADD: in getInstrMapping()
674 case TargetOpcode::G_SUB: in getInstrMapping()
676 case TargetOpcode::G_MUL: in getInstrMapping()
680 case TargetOpcode::G_AND: in getInstrMapping()
681 case TargetOpcode::G_OR: in getInstrMapping()
682 case TargetOpcode::G_XOR: in getInstrMapping()
[all …]
|
| H A D | AArch64PreLegalizerCombiner.cpp | 252 if (I1Opc == TargetOpcode::G_MUL) { in matchExtAddvToUdotAddv()
277 if (I1Opc == TargetOpcode::G_ZEXT) in matchExtAddvToUdotAddv()
424 if (ExtOpc == TargetOpcode::G_ZEXT) in matchExtUaddvToUaddlv()
723 case TargetOpcode::G_CONCAT_VECTORS: in tryCombineAll()
725 case TargetOpcode::G_SHUFFLE_VECTOR: in tryCombineAll()
727 case TargetOpcode::G_UADDO: in tryCombineAll()
729 case TargetOpcode::G_MEMCPY_INLINE: in tryCombineAll()
731 case TargetOpcode::G_MEMCPY: in tryCombineAll()
732 case TargetOpcode::G_MEMMOVE: in tryCombineAll()
733 case TargetOpcode::G_MEMSET: { in tryCombineAll()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | GISelKnownBits.cpp | 40 case TargetOpcode::COPY: in computeKnownAlignment()
206 case TargetOpcode::COPY: in computeKnownBitsImpl()
207 case TargetOpcode::G_PHI: in computeKnownBitsImpl()
208 case TargetOpcode::PHI: { in computeKnownBitsImpl()
267 case TargetOpcode::G_SUB: { in computeKnownBitsImpl()
276 case TargetOpcode::G_XOR: { in computeKnownBitsImpl()
294 case TargetOpcode::G_ADD: { in computeKnownBitsImpl()
303 case TargetOpcode::G_AND: { in computeKnownBitsImpl()
313 case TargetOpcode::G_OR: { in computeKnownBitsImpl()
374 case TargetOpcode::G_FCMP: in computeKnownBitsImpl()
[all …]
|
| H A D | CSEMIRBuilder.cpp | 177 case TargetOpcode::G_ADD: in buildInstr()
179 case TargetOpcode::G_AND: in buildInstr()
180 case TargetOpcode::G_ASHR: in buildInstr()
181 case TargetOpcode::G_LSHR: in buildInstr()
182 case TargetOpcode::G_MUL: in buildInstr()
183 case TargetOpcode::G_OR: in buildInstr()
184 case TargetOpcode::G_SHL: in buildInstr()
185 case TargetOpcode::G_SUB: in buildInstr()
186 case TargetOpcode::G_XOR: in buildInstr()
187 case TargetOpcode::G_UDIV: in buildInstr()
[all …]
|
| H A D | LegalizerHelper.cpp | 2263 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalarMulo()
2567 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalar()
2668 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; in widenScalar()
5666 IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT); in narrowScalarFPTOI()
6439 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; in lowerRotateWithReverseRotate()
6455 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; in lowerRotate()
6461 unsigned FShOpc = IsLeft ? TargetOpcode::G_FSHL : TargetOpcode::G_FSHR; in lowerRotate()
6482 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; in lowerRotate()
6952 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; in lowerFMinNumMaxNum()
8012 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV in lowerDIVREM()
[all …]
|
| H A D | MachineIRBuilder.cpp | 529 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
1131 case TargetOpcode::G_FNEG: in buildInstr()
1132 case TargetOpcode::G_ABS: in buildInstr()
1139 case TargetOpcode::G_ADD: in buildInstr()
1140 case TargetOpcode::G_AND: in buildInstr()
1141 case TargetOpcode::G_MUL: in buildInstr()
1142 case TargetOpcode::G_OR: in buildInstr()
1143 case TargetOpcode::G_SUB: in buildInstr()
1144 case TargetOpcode::G_XOR: in buildInstr()
1165 case TargetOpcode::G_SHL: in buildInstr()
[all …]
|
| H A D | CSEInfo.cpp | 41 case TargetOpcode::G_ADD: in shouldCSEOpc()
42 case TargetOpcode::G_AND: in shouldCSEOpc()
43 case TargetOpcode::G_ASHR: in shouldCSEOpc()
44 case TargetOpcode::G_LSHR: in shouldCSEOpc()
45 case TargetOpcode::G_MUL: in shouldCSEOpc()
46 case TargetOpcode::G_OR: in shouldCSEOpc()
47 case TargetOpcode::G_SHL: in shouldCSEOpc()
48 case TargetOpcode::G_SUB: in shouldCSEOpc()
49 case TargetOpcode::G_XOR: in shouldCSEOpc()
50 case TargetOpcode::G_UDIV: in shouldCSEOpc()
[all …]
|
| H A D | Utils.cpp | 339 case TargetOpcode::COPY: in getConstantVRegValWithLookThrough()
393 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT; in isAnyConstant()
662 case TargetOpcode::G_ADD: in ConstantFoldBinOp()
665 case TargetOpcode::G_AND: in ConstantFoldBinOp()
671 case TargetOpcode::G_MUL: in ConstantFoldBinOp()
673 case TargetOpcode::G_OR: in ConstantFoldBinOp()
675 case TargetOpcode::G_SHL: in ConstantFoldBinOp()
677 case TargetOpcode::G_SUB: in ConstantFoldBinOp()
679 case TargetOpcode::G_XOR: in ConstantFoldBinOp()
820 case TargetOpcode::G_FMA: in isKnownNeverNaN()
[all …]
|
| H A D | CombinerHelper.cpp | 1393 Opcode == TargetOpcode::G_SDIV || Opcode == TargetOpcode::G_SREM; in applyCombineDivRem()
4161 Opc == TargetOpcode::G_FSHL ? TargetOpcode::G_ROTL : TargetOpcode::G_ROTR; in matchFunnelShiftToRotate()
5319 Opc == TargetOpcode::G_FMAD || Opc == TargetOpcode::G_FMA); in matchRedundantNegOperands()
5454 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFMulToFMadOrFMA()
5505 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFpExtFMulToFMadOrFMA()
5563 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFMAFMulToFMadOrFMA()
5632 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5762 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFSubFMulToFMadOrFMA()
5804 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFSubFNegFMulToFMadOrFMA()
5851 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFSubFpExtFMulToFMadOrFMA()
[all …]
|
| H A D | LegacyLegalizerInfo.cpp | 71 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
72 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
73 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
74 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
75 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegacyLegalizerInfo()
77 setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
79 setScalarAction(TargetOpcode::G_INTRINSIC_CONVERGENT, 0, {{1, Legal}}); in LegacyLegalizerInfo()
86 TargetOpcode::G_ADD, 0, widenToLargerTypesAndNarrowToLargest); in LegacyLegalizerInfo()
88 TargetOpcode::G_OR, 0, widenToLargerTypesAndNarrowToLargest); in LegacyLegalizerInfo()
90 TargetOpcode::G_LOAD, 0, narrowToSmallerAndUnsupportedIfTooSmall); in LegacyLegalizerInfo()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 111 case TargetOpcode::G_FADD: in isFloatingPointOpcode()
112 case TargetOpcode::G_FSUB: in isFloatingPointOpcode()
113 case TargetOpcode::G_FMUL: in isFloatingPointOpcode()
114 case TargetOpcode::G_FDIV: in isFloatingPointOpcode()
115 case TargetOpcode::G_FABS: in isFloatingPointOpcode()
116 case TargetOpcode::G_FSQRT: in isFloatingPointOpcode()
117 case TargetOpcode::G_FCEIL: in isFloatingPointOpcode()
119 case TargetOpcode::G_FPEXT: in isFloatingPointOpcode()
133 case TargetOpcode::G_FCMP: in isFloatingPointOpcodeUse()
166 case TargetOpcode::G_LOAD: in isAmbiguous()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86RegisterBankInfo.cpp | 178 case TargetOpcode::G_ADD: in getInstrMapping()
179 case TargetOpcode::G_SUB: in getInstrMapping()
180 case TargetOpcode::G_MUL: in getInstrMapping()
182 case TargetOpcode::G_FADD: in getInstrMapping()
183 case TargetOpcode::G_FSUB: in getInstrMapping()
184 case TargetOpcode::G_FMUL: in getInstrMapping()
185 case TargetOpcode::G_FDIV: in getInstrMapping()
187 case TargetOpcode::G_SHL: in getInstrMapping()
188 case TargetOpcode::G_LSHR: in getInstrMapping()
205 case TargetOpcode::G_FPEXT: in getInstrMapping()
[all …]
|
| H A D | X86InstructionSelector.cpp | 384 case TargetOpcode::G_LOAD: in select()
400 case TargetOpcode::G_ZEXT: in select()
404 case TargetOpcode::G_ICMP: in select()
406 case TargetOpcode::G_FCMP: in select()
425 case TargetOpcode::G_PHI: in select()
427 case TargetOpcode::G_MUL: in select()
430 case TargetOpcode::G_SDIV: in select()
431 case TargetOpcode::G_UDIV: in select()
432 case TargetOpcode::G_SREM: in select()
554 assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) && in selectLoadStoreOp()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVLegalizerInfo.cpp | 28 TargetOpcode::G_ADD,
29 TargetOpcode::G_FADD,
30 TargetOpcode::G_SUB,
31 TargetOpcode::G_FSUB,
32 TargetOpcode::G_MUL,
33 TargetOpcode::G_FMUL,
34 TargetOpcode::G_SDIV,
43 TargetOpcode::G_AND,
44 TargetOpcode::G_OR,
45 TargetOpcode::G_XOR,
[all …]
|
| H A D | SPIRVInstructionSelector.cpp | 308 case TargetOpcode::G_ICMP: in spvSelect()
310 case TargetOpcode::G_FCMP: in spvSelect()
316 case TargetOpcode::G_LOAD: in spvSelect()
321 case TargetOpcode::G_BR: in spvSelect()
326 case TargetOpcode::G_PHI: in spvSelect()
341 case TargetOpcode::G_SMIN: in spvSelect()
343 case TargetOpcode::G_UMIN: in spvSelect()
346 case TargetOpcode::G_SMAX: in spvSelect()
348 case TargetOpcode::G_UMAX: in spvSelect()
351 case TargetOpcode::G_FMA: in spvSelect()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenCommonISel.cpp | 67 case TargetOpcode::G_TRUNC: in MIIsInTerminatorSequence()
68 case TargetOpcode::G_ZEXT: in MIIsInTerminatorSequence()
69 case TargetOpcode::G_ANYEXT: in MIIsInTerminatorSequence()
70 case TargetOpcode::G_SEXT: in MIIsInTerminatorSequence()
71 case TargetOpcode::G_MERGE_VALUES: in MIIsInTerminatorSequence()
72 case TargetOpcode::G_UNMERGE_VALUES: in MIIsInTerminatorSequence()
73 case TargetOpcode::G_CONCAT_VECTORS: in MIIsInTerminatorSequence()
74 case TargetOpcode::G_BUILD_VECTOR: in MIIsInTerminatorSequence()
75 case TargetOpcode::G_EXTRACT: in MIIsInTerminatorSequence()
240 case TargetOpcode::G_TRUNC: in salvageDebugInfoImpl()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 20 namespace TargetOpcode {
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
|