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Searched refs:TSFlags (Results 1 – 25 of 123) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h188 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; } in usesVXRM() argument
191 const uint64_t TSFlags = Desc.TSFlags; in getVLOpNum() local
194 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags)); in getVLOpNum()
196 if (hasVecPolicyOp(TSFlags)) in getVLOpNum()
202 const uint64_t TSFlags = Desc.TSFlags; in getSEWOpNum() local
203 assert(hasSEWOp(TSFlags)); in getSEWOpNum()
205 if (hasVecPolicyOp(TSFlags)) in getSEWOpNum()
218 const uint64_t TSFlags = Desc.TSFlags; in getFRMOpNum() local
219 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags)) in getFRMOpNum()
233 const uint64_t TSFlags = Desc.TSFlags; in getVXRMOpNum() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h413 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
555 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
559 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
575 return get(Opcode).TSFlags & SIInstrFlags::GWS; in isGWS()
619 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
624 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
662 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
700 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
728 return get(Opcode).TSFlags & in isSpillOpcode()
749 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
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H A DSIInstrFormats.td168 let TSFlags{0} = SALU;
169 let TSFlags{1} = VALU;
171 let TSFlags{2} = SOP1;
172 let TSFlags{3} = SOP2;
173 let TSFlags{4} = SOPC;
174 let TSFlags{5} = SOPK;
175 let TSFlags{6} = SOPP;
177 let TSFlags{7} = VOP1;
178 let TSFlags{8} = VOP2;
179 let TSFlags{9} = VOPC;
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H A DR600InstrFormats.td53 let TSFlags{4} = Trig;
54 let TSFlags{5} = Op3;
58 let TSFlags{6} = isVector;
61 let TSFlags{10} = Op1;
62 let TSFlags{11} = Op2;
63 let TSFlags{12} = VTXInst;
64 let TSFlags{13} = TEXInst;
65 let TSFlags{14} = ALUInst;
66 let TSFlags{15} = LDS_1A;
67 let TSFlags{16} = LDS_1A1D;
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H A DAMDGPUInsertDelayAlu.cpp48 if (MI.getDesc().TSFlags & VA_VDST_0) in instructionWaitsForVALU()
63 static DelayType getDelayType(uint64_t TSFlags) { in getDelayType() argument
64 if (TSFlags & SIInstrFlags::TRANS) in getDelayType()
66 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
68 if (TSFlags & SIInstrFlags::SALU) in getDelayType()
355 DelayType Type = getDelayType(MI.getDesc().TSFlags); in runOnMachineBasicBlock()
H A DSIPostRABundler.cpp110 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
116 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
120 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
164 let TSFlags{58} = CVINew;
167 let TSFlags{59} = isCVI;
170 let TSFlags{60} = isHVXALU;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp881 uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags; in emitPrefixImpl() local
956 uint64_t TSFlags = Desc.TSFlags; in emitVEXOpcodePrefix() local
1303 uint64_t TSFlags = Desc.TSFlags; in emitREXPrefix() local
1426 uint64_t TSFlags = Desc.TSFlags; in emitOpcodePrefix() local
1488 uint64_t TSFlags = Desc.TSFlags; in emitPrefix() local
1491 if (X86II::isPseudo(TSFlags)) in emitPrefix()
1505 uint64_t TSFlags = Desc.TSFlags; in encodeInstruction() local
1572 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
1579 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
1587 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
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H A DX86ATTInstPrinter.cpp177 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
183 } else if (Desc.TSFlags & X86II::REX_W) { in printVecCompareInstr()
191 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
193 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
221 if (Desc.TSFlags & X86II::EVEX_B) in printVecCompareInstr()
333 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
336 if (Desc.TSFlags & X86II::REX_W) in printVecCompareInstr()
343 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
345 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
351 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86IntelInstPrinter.cpp156 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
167 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
181 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
183 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
212 if (Desc.TSFlags & X86II::EVEX_B) in printVecCompareInstr()
310 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
321 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
324 if (Desc.TSFlags & X86II::REX_W) in printVecCompareInstr()
331 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
333 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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H A DX86BaseInfo.h894 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
897 inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; } in hasImm() argument
902 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
924 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
944 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
1003 (TSFlags & X86II::EVEX_B) && (TSFlags & X86II::VEX_4V); in hasNewDataDest()
1015 switch (TSFlags & X86II::FormMask) { in getMemoryOperandNo()
1032 return hasNewDataDest(TSFlags); in getMemoryOperandNo()
1257 uint64_t TSFlags = Desc.TSFlags; in canUseApxExtendedReg() local
1270 if (isPseudo(TSFlags)) in canUseApxExtendedReg()
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H A DX86InstPrinterCommon.cpp360 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
363 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
366 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
374 if (TSFlags & X86II::EVEX_NF) in printInstFlags()
379 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitVEXPrefix) in printInstFlags()
386 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitEVEXPrefix) in printInstFlags()
395 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); in printInstFlags()
401 !X86_MC::needsAddressSizeOverride(*MI, STI, MemoryOperand, TSFlags)) { in printInstFlags()
H A DX86EncodingOptimization.cpp37 uint64_t TSFlags = Desc.TSFlags; in optimizeInstFromVEX3ToVEX2() local
38 if (!Desc.isCommutable() || (TSFlags & X86II::EncodingMask) != X86II::VEX || in optimizeInstFromVEX3ToVEX2()
39 (TSFlags & X86II::OpMapMask) != X86II::TB || in optimizeInstFromVEX3ToVEX2()
40 (TSFlags & X86II::FormMask) != X86II::MRMSrcReg || in optimizeInstFromVEX3ToVEX2()
41 (TSFlags & X86II::REX_W) || !(TSFlags & X86II::VEX_4V) || in optimizeInstFromVEX3ToVEX2()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td49 let TSFlags{3...0} = VecInstType;
50 let TSFlags{4...4} = IsSimpleMove;
51 let TSFlags{5...5} = IsLoad;
52 let TSFlags{6...6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9...8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp251 if ((MCID.TSFlags & SIInstrFlags::DS) && in generateWaitCntInfo()
252 (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) { in generateWaitCntInfo()
256 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
272 !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) || in generateWaitCntInfo()
273 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
286 } else if (MCID.TSFlags & SIInstrFlags::SMRD) { in generateWaitCntInfo()
288 } else if (MCID.TSFlags & SIInstrFlags::EXP) { in generateWaitCntInfo()
305 return MCID.TSFlags & SIInstrFlags::MUBUF || in isVMEM()
306 MCID.TSFlags & SIInstrFlags::MTBUF || in isVMEM()
307 MCID.TSFlags & SIInstrFlags::MIMG; in isVMEM()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFormats.td283 let TSFlags{6-0} = FormBits;
284 let TSFlags{8-7} = OpSizeBits;
288 let TSFlags{16-13} = OpMapBits;
289 let TSFlags{17} = hasREX_W;
295 let TSFlags{30-29} = OpEncBits;
296 let TSFlags{38-31} = Opcode;
297 let TSFlags{39} = hasVEX_4V;
298 let TSFlags{40} = hasVEX_L;
299 let TSFlags{41} = hasEVEX_K;
300 let TSFlags{42} = hasEVEX_Z;
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H A DX86InstrFMA3Info.cpp141 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
144 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
148 bool IsFMA3Encoding = ((TSFlags & X86II::EncodingMask) == X86II::VEX && in getFMA3Group()
149 (TSFlags & X86II::OpMapMask) == X86II::T8) || in getFMA3Group()
150 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
151 ((TSFlags & X86II::OpMapMask) == X86II::T8 || in getFMA3Group()
152 (TSFlags & X86II::OpMapMask) == X86II::T_MAP6)); in getFMA3Group()
153 bool IsFMA3Prefix = (TSFlags & X86II::OpPrefixMask) == X86II::PD; in getFMA3Group()
160 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
162 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()
H A DX86CompressEVEX.cpp208 uint64_t TSFlags = MI.getDesc().TSFlags; in CompressEVEXImpl() local
211 if ((TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEVEXImpl()
215 if (TSFlags & (X86II::EVEX_K | X86II::EVEX_L2)) in CompressEVEXImpl()
228 bool IsND = X86II::hasNewDataDest(TSFlags); in CompressEVEXImpl()
229 if (TSFlags & X86II::EVEX_B) in CompressEVEXImpl()
251 switch (NewDesc.TSFlags & X86II::EncodingMask) { in CompressEVEXImpl()
260 assert(IsND && (NewDesc.TSFlags & X86II::EVEX_NF) && in CompressEVEXImpl()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
381 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
406 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
425 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
515 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp32 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
53 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
63 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
112 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset() local
113 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in getBaseOffset()
115 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; in getBaseOffset()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp364 uint64_t TSFlags = MI.getDesc().TSFlags; in getDemanded() local
365 if (RISCVII::hasSEWOp(TSFlags)) { in getDemanded()
367 if (RISCVII::hasVLOp(TSFlags)) in getDemanded()
371 if (!RISCVII::usesMaskPolicy(TSFlags)) in getDemanded()
423 assert(!RISCVII::hasVLOp(TSFlags)); in getDemanded()
859 if (RISCVII::hasVLOp(TSFlags)) { in computeInfoForInstr()
1093 uint64_t TSFlags = MI.getDesc().TSFlags; in transferBefore() local
1094 if (!RISCVII::hasSEWOp(TSFlags)) in transferBefore()
1303 uint64_t TSFlags = MI.getDesc().TSFlags; in emitVSETVLIs() local
1304 if (RISCVII::hasSEWOp(TSFlags)) { in emitVSETVLIs()
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H A DRISCVInstrFormats.td168 let TSFlags{4-0} = format.Value;
175 let TSFlags{10-8} = VLMul;
178 let TSFlags{11} = ForceTailAgnostic;
181 let TSFlags{12} = IsTiedPseudo;
184 let TSFlags{13} = HasSEWOp;
187 let TSFlags{14} = HasVLOp;
190 let TSFlags{15} = HasVecPolicyOp;
196 let TSFlags{17} = UsesMaskPolicy;
203 let TSFlags{18} = IsSignExtendingOpW;
206 let TSFlags{19} = HasRoundModeOp;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp381 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; in decodeOperand_AVLdSt_Any() local
392 if (TSFlags & SIInstrFlags::DS) { in decodeOperand_AVLdSt_Any()
735 if (Res && (MCII->get(MI.getOpcode()).TSFlags & in getInstruction()
752 if (Res && (MCII->get(MI.getOpcode()).TSFlags & in getInstruction()
765 if (Res && (MCII->get(MI.getOpcode()).TSFlags & in getInstruction()
802 if (Res && (MCII->get(MI.getOpcode()).TSFlags & in getInstruction()
961 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { in convertDPP8Inst()
963 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || in convertDPP8Inst()
1029 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; in convertMIMGInst() local
1061 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; in convertMIMGInst()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp134 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
135 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
161 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()

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