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Searched refs:SuperRC (Results 1 – 16 of 16) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1223 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair() local
1224 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1362 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1364 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1413 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSMemLoadImmPair()
1461 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
1516 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair()
1578 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferStorePair()
1628 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeFlatLoadPair()
1676 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeFlatStorePair()
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H A DSIRegisterInfo.h266 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
H A DSIInstrInfo.h110 const TargetRegisterClass *SuperRC,
115 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
H A DSIRegisterInfo.cpp2898 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, in getCompatibleSubRegClass() argument
2903 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
2904 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr; in getCompatibleSubRegClass()
H A DSIInstrInfo.cpp5526 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
5542 Register NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
5555 const MachineOperand &Op, const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
5566 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
5595 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
5596 if (!SuperRC) in isLegalRegOperand()
5599 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
H A DAMDGPUISelDAGToDAG.cpp372 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
377 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
H A DAMDGPUInstructionSelector.cpp3065 const TargetRegisterClass *SuperRC, Register IdxReg, in computeIndirectRegIndex() argument
3079 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex()
H A DSIISelLowering.cpp4358 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset() argument
4361 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp606 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
609 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
617 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
619 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
712 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
713 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
H A DRegAllocGreedy.cpp1339 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1342 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1345 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1441 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1444 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1454 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
H A DTargetLoweringBase.cpp1320 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1322 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1324 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1326 BestRC = SuperRC; in findRepresentativeClass()
H A DMachineVerifier.cpp2342 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
2344 if (!SuperRC) { in visitMachineOperand()
2348 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp583 const TargetRegisterClass *SuperRC = nullptr; in combine() local
585 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
589 SuperRC = &Hexagon::HvxWRRegClass; in combine()
595 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
H A DHexagonRegisterInfo.cpp439 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
440 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.h418 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
419 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h657 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass() argument