Searched refs:SuccPred (Results 1 – 3 of 3) sorted by relevance
868 if (SuccPred == Succ || SuccPred == BB in isProfitableToTailDup()869 || BlockToChain[SuccPred] == &Chain in isProfitableToTailDup()872 auto Freq = MBFI->getBlockFreq(SuccPred) in isProfitableToTailDup()873 * MBPI->getEdgeProbability(SuccPred, Succ); in isProfitableToTailDup()979 for (auto *SuccPred : Succ->predecessors()) { in isTrellis() local981 if (Successors.count(SuccPred)) { in isTrellis()989 if (SuccPred == BB || (BlockFilter && !BlockFilter->count(SuccPred)) || in isTrellis()994 if (!SeenPreds.insert(SuccPred).second) in isTrellis()996 if (!hasSameSuccessors(*SuccPred, Successors)) in isTrellis()1080 if (SuccPred != BB) in getBestTrellisSuccessor()[all …]
2868 for (const SDep &SuccPred : SuccSU->Preds) { in canClobberReachingPhysRegUse() local2869 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()2873 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2874 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()2881 if (TRI->regsOverlap(ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2882 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()
1025 for (BasicBlock *SuccPred : SuccPreds) { in CanRedirectPredsOfEmptyBBToSucc()1026 if (BBPreds.count(SuccPred)) { in CanRedirectPredsOfEmptyBBToSucc()1029 CommonPred = SuccPred; in CanRedirectPredsOfEmptyBBToSucc()