| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPromoteAlloca.cpp | 418 auto *SubVecTy = FixedVectorType::get(VecEltTy, NumLoadedElts); in promoteAllocaUserToVector() local
419 assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy)); in promoteAllocaUserToVector()
421 Value *SubVec = PoisonValue::get(SubVecTy); in promoteAllocaUserToVector()
431 else if (SubVecTy->isPtrOrPtrVectorTy()) in promoteAllocaUserToVector()
432 SubVec = CreateTempPtrIntCast(SubVec, SubVecTy); in promoteAllocaUserToVector()
473 auto *SubVecTy = FixedVectorType::get(VecEltTy, NumWrittenElts); in promoteAllocaUserToVector() local
474 assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy)); in promoteAllocaUserToVector()
476 if (SubVecTy->isPtrOrPtrVectorTy()) in promoteAllocaUserToVector()
477 Val = CreateTempPtrIntCast(Val, SubVecTy); in promoteAllocaUserToVector()
481 Val = Builder.CreateBitOrPointerCast(Val, SubVecTy); in promoteAllocaUserToVector()
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| H A D | AMDGPUCodeGenPrepare.cpp | 1962 Type *SubVecTy = FixedVectorType::get(EltTy, SubVecSize); in visitPHINode() local
1965 Slices.emplace_back(SubVecTy, Idx, SubVecSize); in visitPHINode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 168 Instruction *VecInst, unsigned NumSubVectors, FixedVectorType *SubVecTy, in decompose() argument
177 DL.getTypeSizeInBits(SubVecTy) * NumSubVectors && in decompose()
189 createSequentialMask(Indices[i], SubVecTy->getNumElements(), in decompose()
207 VecBaseTy = SubVecTy; in decompose()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 402 auto *SubVecTy = FixedVectorType::get(Tp->getElementType(), SubVF); in getShuffleCost() local
417 SubVecTy, SubMask, CostKind, 0, nullptr); in getShuffleCost()
599 FixedVectorType *SubVecTy = in getInterleavedMemoryOpCost() local
603 getShuffleCost(TTI::ShuffleKind::SK_PermuteSingleSrc, SubVecTy, Mask, in getInterleavedMemoryOpCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1537 auto *SubVecTy = in getInterleavedMemoryOpCost() local
1546 TLI->isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in getInterleavedMemoryOpCost()
1547 return Factor * BaseCost * TLI->getNumInterleavedAccesses(SubVecTy, DL); in getInterleavedMemoryOpCost()
1556 DL.getTypeSizeInBits(SubVecTy).getFixedValue() <= 64) in getInterleavedMemoryOpCost()
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| H A D | ARMISelLowering.cpp | 21809 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
21817 if (!isLegalInterleavedAccessType(Factor, SubVecTy, Alignment, DL)) in lowerInterleavedStore()
21820 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL); in lowerInterleavedStore()
21837 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
21847 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
21850 assert(isTypeLegal(EVT::getEVT(SubVecTy)) && "Illegal vstN vector type!"); in lowerInterleavedStore()
21861 Type *Tys[] = {PtrTy, SubVecTy}; in lowerInterleavedStore()
21877 Type *Tys[] = {PtrTy, SubVecTy}; in lowerInterleavedStore()
21896 BaseAddr = Builder.CreateConstGEP1_32(SubVecTy->getElementType(), in lowerInterleavedStore()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 3020 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst() local
3024 if (DstTy && VecTy && SubVecTy) { in visitCallInst()
3027 unsigned SubVecNumElts = SubVecTy->getNumElements(); in visitCallInst()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 3251 auto *SubVecTy = in getInterleavedMemoryOpCost() local
3260 TLI->isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in getInterleavedMemoryOpCost()
3261 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in getInterleavedMemoryOpCost()
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| H A D | AArch64ISelLowering.cpp | 15837 auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen); in lowerInterleavedStore() local
15846 !isLegalInterleavedAccessType(SubVecTy, DL, UseScalable)) in lowerInterleavedStore()
15849 unsigned NumStores = getNumInterleavedAccesses(SubVecTy, DL, UseScalable); in lowerInterleavedStore()
15867 SubVecTy = FixedVectorType::get(IntTy, LaneLen); in lowerInterleavedStore()
15873 SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen); in lowerInterleavedStore()
15875 auto *STVTy = UseScalable ? cast<VectorType>(getSVEContainerIRType(SubVecTy)) in lowerInterleavedStore()
15876 : SubVecTy; in lowerInterleavedStore()
15893 if (Factor == 2 && SubVecTy->getPrimitiveSizeInBits() == 64 && in lowerInterleavedStore()
15911 getSVEPredPatternFromNumElements(SubVecTy->getNumElements()); in lowerInterleavedStore()
15915 DL.getTypeSizeInBits(SubVecTy)) in lowerInterleavedStore()
[all …]
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| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 2374 // C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 5901 VectorType *SubVecTy = cast<VectorType>(SubVec->getType()); in visitIntrinsicCall() local
5904 ElementCount SubVecEC = SubVecTy->getElementCount(); in visitIntrinsicCall()
5905 Check(VecTy->getElementType() == SubVecTy->getElementType(), in visitIntrinsicCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1230 MVT SubVecTy = tyVector(ty(Ext), ElemTy); in insertHvxElementReg() local
1231 SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext), in insertHvxElementReg()
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