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Searched refs:SubRegs (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp228 for (auto &[OldSubReg, SRI] : SubRegs) { in getRegClassWithShiftedSubregs()
283 for (auto [SubReg, SRI] : SubRegs) in getRegClassWithShiftedSubregs()
299 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
323 for (auto [SubReg, SRI] : SubRegs) in getMinSizeReg()
327 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
361 auto I = find_if(SubRegs, [&](auto &P) { in updateLiveIntervals()
365 if (I == SubRegs.end()) { in updateLiveIntervals()
396 SubRegs.erase(I); in updateLiveIntervals()
424 SubRegMap SubRegs; in rewriteReg() local
451 auto *NewRC = getMinSizeReg(RC, SubRegs); in rewriteReg()
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H A DAMDGPUInstructionSelector.cpp562 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES() local
568 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
607 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_UNMERGE_VALUES() local
611 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
614 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
3079 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex() local
3083 if (static_cast<unsigned>(Offset) >= SubRegs.size()) in computeIndirectRegIndex()
3084 return std::pair(IdxReg, SubRegs[0]); in computeIndirectRegIndex()
3085 return std::pair(IdxBaseReg, SubRegs[Offset]); in computeIndirectRegIndex()
H A DSIInstrInfo.cpp5946 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR() local
5957 if (SubRegs == 1) { in readlaneVGPRToSGPR()
5965 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
5976 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoDMR.td46 let SubRegs = subregs;
53 let SubRegs = subregs;
61 let SubRegs = subregs;
66 let SubRegs = subregs;
71 let SubRegs = subregs;
H A DPPCRegisterInfoMMA.td22 let SubRegs = subregs;
31 let SubRegs = subregs;
H A DPPCRegisterInfo.td43 let SubRegs = [SubReg];
49 let SubRegs = subregs;
67 let SubRegs = [!cast<FPR>("F"#EvenIndex), !cast<FPR>("F"#!add(EvenIndex, 1))];
83 let SubRegs = [SubReg];
91 let SubRegs = [SubReg];
104 let SubRegs = subregs;
115 let SubRegs = subregs;
122 let SubRegs = [!cast<GP8>("X"#EvenIndex), !cast<GP8>("X"#!add(EvenIndex, 1))];
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp257 for (const auto &SubReg : SubRegs) { in inheritRegUnits()
270 return SubRegs; in computeSubRegs()
299 if (!SubRegs.insert(SR).second) in computeSubRegs()
312 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
357 for (const auto &SubReg : SubRegs) { in computeSubRegs()
448 return SubRegs; in computeSubRegs()
552 for (auto SubReg : SubRegs) in computeSuperRegs()
558 for (auto SubReg : SubRegs) { in computeSuperRegs()
583 for (auto SubReg : SubRegs) in addSubRegsPreOrder()
617 if (Dim != SubRegs->size()) in expand()
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H A DCodeGenRegisters.h189 return SubRegs; in getSubRegs()
282 SubRegMap SubRegs; variable
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td19 let SubRegs = subregs;
35 let SubRegs = subregs;
45 let SubRegs = subregs;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td17 let SubRegs = subregs;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td34 let SubRegs = [subreg];
42 let SubRegs = [subreg];
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h111 uint32_t SubRegs; // Sub-register set, described above member
524 I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td66 let SubRegs = subregs;
87 let SubRegs = subregs;
99 let SubRegs = subregs;
115 let SubRegs = subregs;
169 let SubRegs = [USR_OVF];
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td42 let SubRegs = subregs;
51 let SubRegs = subregs;
58 let SubRegs = subregs;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td22 let SubRegs = SUBREGS;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td110 // in the SubRegs field of a Register definition. For example:
156 // SubRegs - A list of registers that are parts of this register. Note these
158 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
160 list<Register> SubRegs = [];
162 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
164 // SubRegs.
217 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
221 let SubRegs = subregs;
413 // SubRegs - N lists of registers to be zipped up. Super-registers are
414 // synthesized from the first element of each SubRegs list, the second
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp935 unsigned SubRegs = 0; in copyPhysReg() local
942 SubRegs = 2; in copyPhysReg()
946 SubRegs = 4; in copyPhysReg()
951 SubRegs = 2; in copyPhysReg()
955 SubRegs = 3; in copyPhysReg()
959 SubRegs = 4; in copyPhysReg()
963 SubRegs = 2; in copyPhysReg()
967 SubRegs = 2; in copyPhysReg()
972 SubRegs = 3; in copyPhysReg()
977 SubRegs = 4; in copyPhysReg()
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H A DARMRegisterInfo.td20 let SubRegs = subregs;
H A DARMISelDAGToDAG.cpp2932 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; in SelectCDE_CXxD() local
2934 std::swap(SubRegs[0], SubRegs[1]); in SelectCDE_CXxD()
2939 SDValue SubReg = CurDAG->getTargetExtractSubreg(SubRegs[ResIdx], Loc, in SelectCDE_CXxD()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td20 let SubRegs = subregs;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp360 const unsigned SubRegs[]);
1376 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
1379 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1385 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
1388 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1395 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZTuple() local
1398 return createTuple(Regs, RegClassIDs, SubRegs); in createZTuple()
1408 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZMulTuple() local
1410 return createTuple(Regs, RegClassIDs, SubRegs); in createZMulTuple()
1415 const unsigned SubRegs[]) { in createTuple() argument
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H A DAArch64RegisterInfo.td18 let SubRegs = subregs;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp690 const unsigned SubRegs[], MachineIRBuilder &MIB) { in createTuple() argument
702 RegSequence.addImm(SubRegs[I]); in createTuple()
711 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
713 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createDTuple()
720 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
722 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createQTuple()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td18 let SubRegs = subregs;