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Searched refs:SubRegIdx (Results 1 – 25 of 35) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
349 if (SubRegIdx == 0) in computeMainRangesFixFlags()
H A DRegisterPressure.cpp533 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
536 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
541 SubRegIdx = 0; in collectOperandLanes()
545 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
547 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
551 void pushRegLanes(Register Reg, unsigned SubRegIdx, in pushRegLanes() argument
554 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
555 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1232 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1233 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
H A DVirtRegMap.cpp396 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
397 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
398 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
H A DStackMaps.cpp286 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
287 if (SubRegIdx) in parseOperand()
288 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
H A DMachineCopyPropagation.cpp697 unsigned SubRegIdx = TRI->getSubRegIndex(CopyDstReg, MOUse.getReg()); in forwardUses() local
698 assert(SubRegIdx && in forwardUses()
700 ForwardedReg = TRI->getSubReg(CopySrcReg, SubRegIdx); in forwardUses()
703 << TRI->getSubRegIndexName(SubRegIdx) << '\n'); in forwardUses()
H A DRegAllocFast.cpp971 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
972 if (SubRegIdx != 0) { in allocVirtRegUndef()
973 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
H A DMachineVerifier.cpp2511 const unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
2517 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() && in checkLiveness()
2565 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2566 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
2663 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
2664 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
H A DRegisterCoalescer.cpp319 MachineOperand &MO, unsigned SubRegIdx);
1791 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1792 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
1945 unsigned SubRegIdx = MO.getSubReg(); in setUndefOnPrunedSubRegUses() local
1946 if (SubRegIdx == 0 || MO.isUndef()) in setUndefOnPrunedSubRegUses()
1949 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in setUndefOnPrunedSubRegUses()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp291 unsigned Opcode, SubRegIdx; in lowerVSPILL() local
297 SubRegIdx = RISCV::sub_vrm1_0; in lowerVSPILL()
301 SubRegIdx = RISCV::sub_vrm2_0; in lowerVSPILL()
305 SubRegIdx = RISCV::sub_vrm4_0; in lowerVSPILL()
340 .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I)) in lowerVSPILL()
368 unsigned Opcode, SubRegIdx; in lowerVRELOAD() local
374 SubRegIdx = RISCV::sub_vrm1_0; in lowerVRELOAD()
378 SubRegIdx = RISCV::sub_vrm2_0; in lowerVRELOAD()
382 SubRegIdx = RISCV::sub_vrm4_0; in lowerVRELOAD()
413 TRI->getSubReg(DestReg, SubRegIdx + I)) in lowerVRELOAD()
H A DRISCVISelDAGToDAG.cpp371 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG() local
373 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
412 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEGFF() local
414 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
464 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLXSEG() local
2009 unsigned SubRegIdx; in Select() local
2010 std::tie(SubRegIdx, Idx) = in Select()
2031 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
2062 unsigned SubRegIdx; in Select() local
2063 std::tie(SubRegIdx, Idx) = in Select()
[all …]
H A DRISCVInstrInfo.cpp306 unsigned SubRegIdx; in copyPhysRegVector() local
313 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysRegVector()
319 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysRegVector()
325 SubRegIdx = RISCV::sub_vrm4_0; in copyPhysRegVector()
332 SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0. in copyPhysRegVector()
385 BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I)); in copyPhysRegVector()
387 MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef); in copyPhysRegVector()
391 MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I), in copyPhysRegVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp144 unsigned SubRegIdx) const;
188 unsigned SubRegIdx) const { in getSuperRegClassMask()
190 SuperRegMasks.try_emplace({RC, SubRegIdx}, nullptr); in getSuperRegClassMask()
193 if (RCI.getSubReg() == SubRegIdx) { in getSuperRegClassMask()
H A DSILoadStoreOptimizer.cpp1430 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeSMemLoadImmPair()
1431 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeSMemLoadImmPair()
1485 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeBufferLoadPair()
1486 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeBufferLoadPair()
1544 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferLoadPair()
1545 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferLoadPair()
1573 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferStorePair()
1574 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferStorePair()
1642 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeFlatLoadPair()
1643 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeFlatLoadPair()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td518 SubRegIndex SubRegIdx, Operand IndexType,
522 (STR (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
527 SubRegIndex SubRegIdx, Instruction STR> {
528 defm : VecStoreLane64_0Pat<am_unscaled64, StoreOp, VTy, STy, SubRegIdx, simm9, STR>;
533 SubRegIndex SubRegIdx,
538 (STRW (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
543 (STRX (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp330 const unsigned *SubRegIdx, in copyPhysSubRegs() argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); in copyPhysSubRegs()
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg() local
396 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local
402 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp196 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
202 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
H A DX86ISelDAGToDAG.cpp1640 unsigned SubRegIdx = N->getConstantOperandVal(2); in PostprocessISelDAG() local
1641 if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) in PostprocessISelDAG()
5903 unsigned SubRegIdx; in Select() local
5919 SubRegIdx = 0; in Select()
5927 SubRegIdx = 0; in Select()
5936 SubRegIdx = X86::sub_8bit; in Select()
5942 SubRegIdx = X86::sub_16bit; in Select()
5948 SubRegIdx = X86::sub_32bit; in Select()
5959 if (SubRegIdx != 0) { in Select()
5961 CurDAG->getTargetExtractSubreg(SubRegIdx, dl, SubRegVT, Shift); in Select()
H A DX86InstrAVX512.td2982 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
2983 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx)),
3006 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3025 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3494 Narrow.SubRegIdx)>;
3503 Narrow.SubRegIdx)>;
10369 _.RC:$src, _.SubRegIdx)),
11194 _.info256.SubRegIdx)),
11195 _.info256.SubRegIdx)>;
11202 _.info128.SubRegIdx)),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h1072 uint16_t SubRegIdx = readU16(); in executeMatchTable() local
1075 0, SubRegIdx); in executeMatchTable()
1079 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()
1246 uint16_t SubRegIdx = readU16(); in executeMatchTable() local
1250 MI->getOperand(MI->getNumOperands() - 1).setSubReg(SubRegIdx); in executeMatchTable()
1255 << RenderOpID << ", " << SubRegIdx << ")\n"); in executeMatchTable()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp475 CodeGenSubRegIndex *SubRegIdx; in computeSecondarySubRegs() local
477 std::tie(SubRegIdx, SubReg) = SubRegQueue.front(); in computeSecondarySubRegs()
495 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
497 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
498 if (SubRegIdx->ConcatenationOf.empty()) in computeSecondarySubRegs()
499 Parts.push_back(SubRegIdx); in computeSecondarySubRegs()
501 append_range(Parts, SubRegIdx->ConcatenationOf); in computeSecondarySubRegs()
H A DGlobalISelMatchTable.cpp1948 const bool NeedsFlags = (SubRegIdx || IsDef); in emitRenderOpcodes()
1949 if (SubRegIdx) { in emitRenderOpcodes()
1975 if (SubRegIdx) in emitRenderOpcodes()
1976 Table << MatchTable::NamedValue(2, SubRegIdx->getQualifiedName()); in emitRenderOpcodes()
2009 ImmRenderer::emitAddImm(Table, Rule, InsnID, SubRegIdx->EnumValue, in emitRenderOpcodes()
H A DGlobalISelMatchTable.h2038 const CodeGenSubRegIndex *SubRegIdx; variable
2047 SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {} in OperandRenderer()
2088 const CodeGenSubRegIndex *SubRegIdx; variable
2092 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h658 unsigned SubRegIdx) const { in getSubRegisterClass() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2151 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local
2156 SubRegIdx), 0); in ExtendToInt64()
2165 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local
3236 SDValue SubRegIdx = in addExtOrTrunc() local
3239 ImDef, NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
3246 SDValue SubRegIdx = in addExtOrTrunc() local
3249 NatWidthRes, SubRegIdx), 0); in addExtOrTrunc()
5406 SDValue SubRegIdx = CurDAG->getTargetConstant(SubReg, dl, MVT::i32); in Select() local
5409 CR6Reg, SubRegIdx, BCDOp.getValue(1)), in Select()
5459 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_eq, dl, MVT::i32); in Select() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1183 unsigned SubRegIdx = in loadVectorConstant() local
1186 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()

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