| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 373 def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
1186 def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>;
1189 def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>;
1192 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>;
1195 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>;
1199 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
1202 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
1362 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>;
1363 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>;
1364 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>;
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 68 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
69 if (Srl.getOpcode() == ISD::SRL) { in isExtractHiElt()
70 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt()
72 Out = stripBitcast(Srl.getOperand(0)); in isExtractHiElt()
2252 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
2253 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); in SelectS_BFE()
2262 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
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| H A D | SIISelLowering.cpp | 13173 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
13175 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
13178 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, VecEltAsIntVT, Srl); in performExtractVectorEltCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 464 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
466 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) || in PreprocessISelDAG()
485 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
486 Srl.getOperand(0), in PreprocessISelDAG()
487 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), in PreprocessISelDAG()
490 Srl, in PreprocessISelDAG()
491 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
493 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2006 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); in foldMaskAndShiftToExtract() local
2007 SDValue And = DAG.getNode(ISD::AND, DL, XVT, Srl, NewMask); in foldMaskAndShiftToExtract()
2019 insertDAGNode(DAG, N, Srl); in foldMaskAndShiftToExtract()
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| H A D | X86ISelLowering.cpp | 29913 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, R, in LowerRotate() local
29915 return DAG.getNode(ISD::OR, DL, VT, Shl, Srl); in LowerRotate()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17042 SDValue Srl = And.getOperand(0); in performMulVectorCmpZeroCombine() local
17047 !ISD::isConstantSplatVector(Srl.getOperand(1).getNode(), V3)) in performMulVectorCmpZeroCombine()
17060 SDValue In = DAG.getNode(AArch64ISD::NVCAST, DL, HalfVT, Srl.getOperand(0)); in performMulVectorCmpZeroCombine()
20826 static SDValue trySimplifySrlAddToRshrnb(SDValue Srl, SelectionDAG &DAG, in trySimplifySrlAddToRshrnb() argument
20828 EVT VT = Srl->getValueType(0); in trySimplifySrlAddToRshrnb()
20831 Srl->getOpcode() != ISD::SRL) in trySimplifySrlAddToRshrnb()
20845 dyn_cast_or_null<ConstantSDNode>(DAG.getSplatValue(Srl->getOperand(1))); in trySimplifySrlAddToRshrnb()
20852 SDValue Add = Srl->getOperand(0); in trySimplifySrlAddToRshrnb()
20863 SDLoc DL(Srl); in trySimplifySrlAddToRshrnb()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6720 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local
6726 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); in lowerFPTOSI()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12662 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); in performTRUNCATECombine() local
12663 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Srl); in performTRUNCATECombine()
12690 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); in performANDCombine() local
12691 SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Srl, in performANDCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4845 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
4846 AddToWorklist(Srl.getNode()); in visitSDIVLike()
4847 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); in visitSDIVLike()
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| /freebsd-14.2/share/misc/ |
| H A D | usb_vendors | 18254 152b MIR Srl
22261 25dd Bit4id Srl
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| H A D | pci_vendors | 24821 1ab9 Espia Srl
|