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Searched refs:Src1VT (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td2152 ValueType Src1VT> {
2159 !if(!eq(Src1VT.Size, 64),
2169 ValueType Src1VT = i32> {
2176 !if(!eq(Src1VT.Size, 64),
2192 ValueType Src1VT = i32> {
2198 ValueType Src1VT = i32> {
2205 ValueType Src1VT = i32> {
2254 field ValueType Src1VT = ArgVT[2];
2275 field Operand Src1Mod = getSrcMod<Src1VT>.ret;
2306 field bit HasSrc1FloatMods = Src1VT.isFP;
[all …]
H A DVOPInstructions.td1070 !subst(P.Src1RC32, P.Src1VT, tmp))));
1122 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1127 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
1141 dag src1_dag = (P.Src1VT (SrcPat P.Src1VT:$src1, i32:$src1_modifiers));
1168 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
1173 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
1187 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
1193 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
1204 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
1229 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
[all …]
H A DVOP3PInstructions.td856 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)),
865 (P.Src1VT P.Src1VT:$src1),
874 (VOP3PModsNeg i32:$src1_modifiers), (P.Src1VT P.Src1VT:$src1),
1112 …dag Src1InPat = !cond(IsAB_F16 : (ins (Src1VT (WMMAModsF16Neg Src1VT:$src1, i32:$src1_modifiers)…
1113 IsAB_BF16 : (ins Src1VT:$src1),
1114 IsIU : (ins (VOP3PModsNeg i32:$src1_modifiers), Src1VT:$src1),
1115 IsFP8BF8 : (ins Src1VT:$src1));
1116 dag Src1OutPat = !cond(IsAB_F16 : (ins i32:$src1_modifiers, Src1VT:$src1),
1117 IsAB_BF16 : (ins (i32 8), Src1VT:$src1),
1118 IsIU : (ins i32:$src1_modifiers, Src1VT:$src1),
[all …]
H A DVOPCInstructions.td53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
91 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
93 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
96 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
121 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
123 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
126 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
260 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
262 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
798 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
[all …]
H A DVOP2Instructions.td137 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
444 (ins !if(!eq(Src1VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0Y,
490 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
493 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
817 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
826 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
931 (i16 (VOP3Mods0 P.Src1VT:$src1, i32:$src1_modifiers)))),
H A DVOP3Instructions.td958 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
959 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
967 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
968 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1444 MVT Src1VT = Src1.getSimpleValueType(); in Select() local
1446 switch (RISCVTargetLowering::getLMUL(Src1VT)) { in Select()
1466 Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT); in Select()
1503 MVT Src1VT = Src1.getSimpleValueType(); in Select() local
1506 switch (RISCVTargetLowering::getLMUL(Src1VT)) { in Select()
1545 Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT); in Select()