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Searched refs:Src0VT (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOPInstructions.td1140 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers));
1167 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
1172 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
1176 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))];
1185 …(DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
1191 …(DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
1192 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
1196 … (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))];
1215 (VOP3Mods0 P.Src0VT:$src0))
1237 list<dag> ret = !if(!eq(P.Src0VT, P.Src1VT),
[all …]
H A DSIInstrInfo.td2157 !if(!eq(Src0VT.Size, 64),
2174 !if(!eq(Src0VT.Size, 64),
2226 !if(!eq(Src0VT.Size, 64),
2253 field ValueType Src0VT = ArgVT[1];
2274 field Operand Src0Mod = getSrcMod<Src0VT>.ret;
2277 field Operand Src0ModDPP = getSrcModDPP<Src0VT>.ret;
2305 field bit HasSrc0FloatMods = Src0VT.isFP;
2309 field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
2321 field bit IsPacked = Src0VT.isVector;
2469 let Src0Mod = getSrcMod<Src0VT, 1 /*IsTrue16*/>.ret;
[all …]
H A DVOP3PInstructions.td855 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)),
864 (P.Src0VT P.Src0VT:$src0),
873 (VOP3PModsNeg i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0),
1104 …dag Src0InPat = !cond(IsAB_F16 : (ins (Src0VT (WMMAModsF16Neg Src0VT:$src0, i32:$src0_modifiers)…
1105 IsAB_BF16 : (ins Src0VT:$src0),
1106 IsIU : (ins (VOP3PModsNeg i32:$src0_modifiers), Src0VT:$src0),
1107 IsFP8BF8 : (ins Src0VT:$src0));
1108 dag Src0OutPat = !cond(IsAB_F16 : (ins i32:$src0_modifiers, Src0VT:$src0),
1109 IsAB_BF16 : (ins (i32 8), Src0VT:$src0),
1110 IsIU : (ins i32:$src0_modifiers, Src0VT:$src0),
[all …]
H A DVOPCInstructions.td53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
92 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
95 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
122 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
125 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
149 let ReadsModeReg = P.Src0VT.isFP;
256 (setcc (P.Src0VT
262 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
797 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
824 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
[all …]
H A DVOP2Instructions.td72 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
133 (node (P.Src0VT
136 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
440 (ins !if(!eq(Src0VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0X,
489 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
492 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
630 let Src0Mod = !if(!eq(Src0VT.Size, 16), FP16InputMods, FP32InputMods);
817 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
826 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
[all …]
H A DVOP1Instructions.td51 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
110 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
112 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
114 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOP3Instructions.td958 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
959 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
960 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
967 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
968 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
969 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp3119 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT() local
3129 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT); in SplitVecOp_VSELECT()
3142 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()