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Searched refs:SplitScalar (Results 1 – 16 of 16) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp989 std::tie(Lo, Hi) = DAG.SplitScalar(Pair, dl, NVT, NVT); in GetPairElements()
H A DTargetLowering.cpp7672 std::tie(LL, LH) = DAG.SplitScalar(N->getOperand(0), dl, HiLoVT, HiLoVT); in expandDIVREMByConstant()
7747 std::tie(QuotL, QuotH) = DAG.SplitScalar(Quotient, dl, HiLoVT, HiLoVT); in expandDIVREMByConstant()
H A DSelectionDAG.cpp12261 std::pair<SDValue, SDValue> SelectionDAG::SplitScalar(const SDValue &N, in SplitScalar() function in SelectionDAG
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1995 std::tie(LHS_Lo, LHS_Hi) = DAG.SplitScalar(LHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
1999 std::tie(RHS_Lo, RHS_Hi) = DAG.SplitScalar(RHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2059 DAG.SplitScalar(Mulhi1, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2072 DAG.SplitScalar(Mulhi2, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2085 std::tie(Mul3_Lo, Mul3_Hi) = DAG.SplitScalar(Mul3, DL, HalfVT, HalfVT); in LowerUDIVREM64()
H A DSIISelLowering.cpp9901 auto [LowHalf, HighHalf] = DAG.SplitScalar(Pointer, Loc, MVT::i32, MVT::i32); in lowerPointerAsRsrcIntrin()
13458 std::tie(AccumLo, AccumHi) = DAG.SplitScalar(Accum, SL, MVT::i32, MVT::i32); in tryFoldToMad64_32()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp1234 DAG.SplitScalar(Op.getOperand(0), DL, MVT::i32, MVT::i32); in lowerBITCAST()
1279 std::tie(InLo, InHi) = DAG.SplitScalar(In, DL, MVT::i32, MVT::i32); in initAccumulator()
H A DMipsISelLowering.cpp1033 CurDAG.SplitScalar(AddOperand, DL, MVT::i32, MVT::i32); in performMADD_MSUBCombine()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h2245 std::pair<SDValue, SDValue> SplitScalar(const SDValue &N, const SDLoc &DL,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp727 std::tie(Lo, Hi) = DAG.SplitScalar(Arg, DL, MVT::i32, MVT::i32); in Passv64i1ArgInRegs()
H A DX86ISelLowering.cpp22150 auto SplitLHS = DAG.SplitScalar(DAG.getBitcast(IntVT, MaskBits(LHS)), DL, in LowerVectorAllEqual()
22152 auto SplitRHS = DAG.SplitScalar(DAG.getBitcast(IntVT, MaskBits(RHS)), DL, in LowerVectorAllEqual()
25135 std::tie(Lo, Hi) = DAG.SplitScalar(Mask, dl, MVT::i32, MVT::i32); in getMaskNode()
30811 std::tie(Lo, Hi) = DAG.SplitScalar(Src, dl, MVT::i32, MVT::i32); in LowerBITCAST()
32855 DAG.SplitScalar(N->getOperand(2), dl, HalfT, HalfT); in ReplaceNodeResults()
32863 DAG.SplitScalar(N->getOperand(3), dl, HalfT, HalfT); in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3446 std::tie(Lo, Hi) = DAG.SplitScalar(WriteValue, DL, MVT::i32, MVT::i32); in LowerWRITE_REGISTER()
4140 std::tie(Lo, Hi) = DAG.SplitScalar(Operand, dl, VTy, VTy); in LowerINTRINSIC_WO_CHAIN()
6264 std::tie(Lo, Hi) = DAG.SplitScalar(Op, dl, MVT::i32, MVT::i32); in ExpandBITCAST()
6730 DAG.SplitScalar(N->getOperand(0), dl, MVT::i32, MVT::i32); in Expand64BitShift()
6749 std::tie(Lo, Hi) = DAG.SplitScalar(N->getOperand(0), dl, MVT::i32, MVT::i32); in Expand64BitShift()
10084 std::tie(Lo, Hi) = DAG.SplitScalar(Op, DL, MVT::i32, MVT::i32); in WinDBZCheckDenominator()
10455 auto [VLo, VHi] = DAG.SplitScalar(V, dl, MVT::i32, MVT::i32); in createGPRPairNode()
10696 std::tie(Lo, Hi) = DAG.SplitScalar(N->getOperand(3), dl, MVT::i32, MVT::i32); in ReplaceLongIntrinsic()
13748 std::tie(Ops[0], Ops[1]) = DAG.SplitScalar(NA, dl, MVT::i32, MVT::i32); in PerformADDVecReduce()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3202 std::tie(BottomHalf, TopHalf) = DAG.SplitScalar(MulResult, dl, VT, VT); in LowerUMULO_SMULO()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5940 auto StoreValue = DAG.SplitScalar(Value, DL, MVT::i64, MVT::i64); in LowerStore128()
6416 DAG.SplitScalar(Op.getOperand(2), DL, MVT::i64, MVT::i64); in LowerOperation()
24524 auto [VLo, VHi] = DAG.SplitScalar(V, dl, MVT::i64, MVT::i64); in createGPRPairNode()
24610 auto Desired = DAG.SplitScalar(N->getOperand(2), DL, MVT::i64, MVT::i64); in ReplaceCMP_SWAP_128Results()
24611 auto New = DAG.SplitScalar(N->getOperand(3), DL, MVT::i64, MVT::i64); in ReplaceCMP_SWAP_128Results()
24722 DAG.SplitScalar(Val128, SDLoc(Val128), MVT::i64, MVT::i64); in ReplaceATOMIC_LOAD_128Results()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3991 std::tie(Lo, Hi) = DAG.SplitScalar(Scalar, DL, MVT::i32, MVT::i32); in splatSplitI64WithVL()
5911 std::tie(Lo, Hi) = DAG.SplitScalar(Op0, DL, MVT::i32, MVT::i32); in LowerOperation()
8008 std::tie(ValLo, ValHi) = DAG.SplitScalar(Val, DL, MVT::i32, MVT::i32); in lowerINSERT_VECTOR_ELT()
8307 DAG.SplitScalar(ScalarOp, DL, MVT::i32, MVT::i32); in lowerVectorIntrinsicScalars()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1526 std::tie(Lo, Hi) = DAG.SplitScalar(In, DL, MVT::i64, MVT::i64); in lowerI128ToGR128()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8328 std::tie(Lo, Hi) = DAG.SplitScalar(Src, dl, MVT::f64, MVT::f64); in LowerFP_TO_INT()