| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocBasic.cpp | 230 const LiveInterval &Spill = *Intfs[i]; in spillInterferences() local
233 if (!VRM->hasPhys(Spill.reg())) in spillInterferences()
238 Matrix->unassign(Spill); in spillInterferences()
241 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in spillInterferences()
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| H A D | StackFrameLayoutAnalysisPass.cpp | 53 Spill, // a Spill slot enumerator
71 SlotTy = SlotType::Spill; in SlotData()
116 case SlotType::Spill: in getTypeString()
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| H A D | InlineSpiller.cpp | 144 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1127 MachineBasicBlock::iterator Spill = std::next(MI); in insertSpill() local
1128 LIS.InsertMachineInstrRangeInMaps(Spill, MIS.end()); in insertSpill()
1129 for (const MachineInstr &MI : make_range(Spill, MIS.end())) in insertSpill()
1138 if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1) in insertSpill()
1326 SlotIndex Idx = LIS.getInstructionIndex(Spill); in addToMergeableSpills()
1329 MergeableSpills[MIdx].insert(&Spill); in addToMergeableSpills()
1339 SlotIndex Idx = LIS.getInstructionIndex(Spill); in rmFromMergeableSpills()
1342 return MergeableSpills[MIdx].erase(&Spill); in rmFromMergeableSpills()
1431 for (auto *const Spill : Spills) { in getVisitOrders() local
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| H A D | MachineCopyPropagation.cpp | 1188 for (const MachineInstr *Spill : drop_begin(SC)) in EliminateSpillageCopies() local
1189 if (CopySourceInvalid.count(Spill)) in EliminateSpillageCopies()
1254 auto IsSpillReloadPair = [&, this](const MachineInstr &Spill, in EliminateSpillageCopies()
1256 if (!IsFoldableCopy(Spill) || !IsFoldableCopy(Reload)) in EliminateSpillageCopies()
1259 isCopyInstr(Spill, *TII, UseCopyInstr); in EliminateSpillageCopies()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 108 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
270 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in saveToVGPRLane() local
272 assert(Spill.size() == NumSubRegs); in saveToVGPRLane()
279 Spill[I].VGPR) in saveToVGPRLane()
281 .addImm(Spill[I].Lane) in saveToVGPRLane()
316 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in restoreFromVGPRLane() local
318 assert(Spill.size() == NumSubRegs); in restoreFromVGPRLane()
325 .addReg(Spill[I].VGPR) in restoreFromVGPRLane()
326 .addImm(Spill[I].Lane); in restoreFromVGPRLane()
974 Spill.first == FramePtrReg ? FramePtrRegScratchCopy : Spill.first; in emitCSRSpillStores()
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| H A D | SIMachineFunctionInfo.cpp | 449 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
452 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
453 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
457 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
465 Spill.FullyAllocated = true; in allocateVGPRSpillToAGPR()
493 Spill.FullyAllocated = false; in allocateVGPRSpillToAGPR()
500 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
503 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
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| H A D | SIMachineFunctionInfo.h | 933 void setHasSpilledSGPRs(bool Spill = true) {
934 HasSpilledSGPRs = Spill;
941 void setHasSpilledVGPRs(bool Spill = true) {
942 HasSpilledVGPRs = Spill;
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| H A D | SIRegisterInfo.cpp | 1778 SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
1788 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR) in spillSGPR()
1790 .addImm(Spill.Lane) in spillSGPR()
1791 .addReg(Spill.VGPR); in spillSGPR()
1895 SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
1898 .addReg(Spill.VGPR) in restoreSGPR()
1899 .addImm(Spill.Lane); in restoreSGPR()
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| /freebsd-14.2/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_powerpc64_asm.S | 8 # Spill r3-r10, f1-f13, and vsr34-vsr45, which are parameter registers.
149 # Spill r3-r4, f1-f8, and vsr34-vsr41, which are return registers.
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.h | 770 unsigned getLocID(SpillLocationNo Spill, unsigned SpillSubReg) {
773 return getLocID(Spill, {Size, Offs});
779 unsigned getLocID(SpillLocationNo Spill, StackSlotPos Idx) {
780 unsigned SlotNo = Spill.id() - 1;
790 unsigned getSpillIDWithIdx(SpillLocationNo Spill, unsigned Idx) {
791 unsigned SlotNo = Spill.id() - 1;
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| H A D | InstrRefBasedImpl.cpp | 1234 const SpillLoc &Spill = SpillLocs[SpillID.id()]; in emitLoc() local
1235 unsigned Base = Spill.SpillBase; in emitLoc()
1265 TRI.getOffsetOpcodes(Spill.SpillOffset, OffsetOps); in emitLoc()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FunctionLoweringInfo.h | 105 Spill, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | StatepointLowering.cpp | 184 if (Record.type != RecordType::Spill) in findPreviousSpillSlot()
923 Record.type = RecordType::Spill; in LowerAsSTATEPOINT()
1252 if (Record.type == RecordType::Spill) { in visitGCRelocate()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 75 int SpillSize = SS; // Spill slot size in bits.
76 int SpillAlignment = SA; // Spill slot alignment in bits.
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| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_sme.td | 640 // Spill and fill of ZT0
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SMEInstrInfo.td | 120 // Spill + fill
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| H A D | AArch64SVEInstrInfo.td | 1594 // Fill/Spill
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAArch64.td | 2787 // Spill + fill
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