| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 89 bool InstCombinerImpl::SimplifyDemandedBits(Instruction *I, unsigned OpNo, in SimplifyDemandedBits() function in InstCombinerImpl 208 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) || in SimplifyDemandedUseBits() 238 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) || in SimplifyDemandedUseBits() 280 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) || in SimplifyDemandedUseBits() 281 SimplifyDemandedBits(I, 0, DemandedMask, LHSKnown, Depth + 1)) in SimplifyDemandedUseBits() 376 SimplifyDemandedBits(I, 1, DemandedMask, LHSKnown, Depth + 1)) in SimplifyDemandedUseBits() 850 if (SimplifyDemandedBits(I, 0, Mask2, LHSKnown, Depth + 1)) in SimplifyDemandedUseBits() 877 if (SimplifyDemandedBits(I, 0, AllOnes, LHSKnown, Depth + 1) || in SimplifyDemandedUseBits() 878 SimplifyDemandedBits(I, 1, AllOnes, RHSKnown, Depth + 1)) in SimplifyDemandedUseBits() 938 SimplifyDemandedBits( in SimplifyDemandedUseBits() [all …]
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| H A D | InstCombineInternal.h | 541 bool SimplifyDemandedBits(Instruction *I, unsigned Op,
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| H A D | InstCombineCompares.cpp | 6127 if (SimplifyDemandedBits(&I, 0, getDemandedBitsLHSMask(I, BitWidth), in foldICmpUsingKnownBits() 6131 if (SimplifyDemandedBits(&I, 1, APInt::getAllOnes(BitWidth), Op1Known, 0)) in foldICmpUsingKnownBits()
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| H A D | InstCombineCalls.cpp | 2018 if (SimplifyDemandedBits(II, 2, Op2Demanded, Op2Known)) in visitCallInst()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 621 bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO); in SimplifyDemandedBits() 638 SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO); in SimplifyDemandedBits() 1079 bool TargetLowering::SimplifyDemandedBits( in SimplifyDemandedBits() function in TargetLowering 1424 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, in SimplifyDemandedBits() 2126 if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO, in SimplifyDemandedBits() 2156 if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts, in SimplifyDemandedBits() 2539 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO, in SimplifyDemandedBits() 2702 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, in SimplifyDemandedBits() 2726 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, in SimplifyDemandedBits() 2780 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, KnownOp0, TLO, in SimplifyDemandedBits() [all …]
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| H A D | DAGCombiner.cpp | 330 bool SimplifyDemandedBits(SDValue Op) { in SimplifyDemandedBits() function in __anonffc06dc60111::DAGCombiner 2906 if (SimplifyDemandedBits(SDValue(N, 0))) in visitADDLike() 4596 if (SimplifyDemandedBits(SDValue(N, 0))) in visitMUL() 5218 if (SimplifyDemandedBits(SDValue(N, 0))) in visitMULHU() 5748 if (SimplifyDemandedBits(SDValue(N, 0))) in visitIMINMAX() 7286 if (SimplifyDemandedBits(SDValue(N, 0))) in visitAND() 7997 if (SimplifyDemandedBits(SDValue(N, 0))) in visitOR() 9591 if (SimplifyDemandedBits(SDValue(N, 0))) in visitXOR() 9804 if (SimplifyDemandedBits(SDValue(N, 0))) in visitRotate() 10119 if (SimplifyDemandedBits(SDValue(N, 0))) in visitSHL() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Transforms/InstCombine/ |
| H A D | InstCombiner.h | 542 virtual bool SimplifyDemandedBits(Instruction *I, unsigned OpNo,
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3873 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 3880 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 3887 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 3892 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1514 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO)) in PerformDAGCombine() 1530 TLI.SimplifyDemandedBits(Time, DemandedMask, Known, TLO)) in PerformDAGCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 189 if (IC.SimplifyDemandedBits(&II, 0, APInt::getLowBitsSet(32, 16), in instCombineIntrinsic() 222 if (IC.SimplifyDemandedBits(&II, CarryOp, APInt::getOneBitSet(32, 29), in instCombineIntrinsic()
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| H A D | ARMISelLowering.cpp | 15204 if (TLI.SimplifyDemandedBits(Op0, DemandedMask, DCI)) in PerformVMOVhrCombine() 15408 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI)) in PerformPREDICATE_CASTCombine() 17639 if (SimplifyDemandedBits(N->getOperand(3), DemandedMask, DCI)) in PerformIntrinsicCombine() 17656 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformIntrinsicCombine() 18979 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine() 18986 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine() 18998 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine() 19007 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) || in PerformDAGCombine() 19008 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI))) in PerformDAGCombine() 19017 if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) || in PerformDAGCombine() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41859 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, in SimplifyDemandedBitsForTargetNode() 42193 if (SimplifyDemandedBits(Op1, LoMask, Known, TLO, Depth + 1)) in SimplifyDemandedBitsForTargetNode() 47691 if (TLI.SimplifyDemandedBits(SDValue(N, 0), in combineVectorInsert() 48748 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) || in combineAnd() 48749 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) { in combineAnd() 50279 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) { in combineMaskedLoad() 50353 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) { in combineMaskedStore() 52285 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) || in combineAndnp() 52286 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) { in combineAndnp() 53290 if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) { in combineX86GatherScatter() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.td | 1983 // occurs because SimplifyDemandedBits prefers srl over sra. 1988 // SimplifyDemandedBits.
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| H A D | RISCVISelLowering.cpp | 15141 if (!SimplifyDemandedBits(Op, Mask, DCI)) in PerformDAGCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3694 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI)) in simplifyMul24() 3696 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI)) in simplifyMul24() 5180 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) { in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 14322 if (TLI.SimplifyDemandedBits(Src, DemandedBits, DCI)) { in performCvtF32UByteNCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 21079 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI)) in performVectorShiftCombine() 21228 if (TLI.SimplifyDemandedBits(Addr, DemandedMask, Known, TLO)) { in performTBISimplification()
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