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Searched refs:ShiftedVal (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp178 uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros; in generateInstSeqLeadingZeros() local
182 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros); in generateInstSeqLeadingZeros()
185 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeqLeadingZeros()
195 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros); in generateInstSeqLeadingZeros()
197 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeqLeadingZeros()
233 int64_t ShiftedVal = Val >> TrailingZeros; in generateInstSeq() local
239 isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion); in generateInstSeq()
241 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeq()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp227 auto ShiftedVal = B.buildShl(Ty, LHS, Shift); in matchAArch64MulConstCombine() local
229 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS; in matchAArch64MulConstCombine()
230 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0); in matchAArch64MulConstCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DInstrProfiling.cpp1004 auto *ShiftedVal = Builder.CreateShl(Builder.getInt8(0x1), BitToSet); in lowerMCDCTestVectorBitmapUpdate() local
1012 auto *Result = Builder.CreateOr(Bitmap, ShiftedVal); in lowerMCDCTestVectorBitmapUpdate()
1036 auto *ShiftedVal = Builder.CreateShl(CondV_32, Update->getCondID()); in lowerMCDCCondBitmapUpdate() local
1040 auto *Result = Builder.CreateOr(Temp, ShiftedVal); in lowerMCDCCondBitmapUpdate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4393 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
4397 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4398 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
4401 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
4404 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
4405 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
4406 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
4410 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4417 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
4418 if (!CanShrinkImmediate(ShiftedVal)) in tryShrinkShlLogicImm()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1001 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
1002 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
1014 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
1015 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1905 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1906 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1907 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1920 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1921 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1922 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp655 int64_t ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm() local
656 if (!isInt<12>(ShiftedVal)) in tryShrinkShlLogicImm()
676 CurDAG->getTargetConstant(ShiftedVal, DL, VT)); in tryShrinkShlLogicImm()