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Searched refs:ShiftVal (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp289 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
290 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
293 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
310 ShiftVal = 12; in getAddSubImmOpValue()
312 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
629 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
630 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
635 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
656 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
657 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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H A DAArch64InstPrinter.cpp1277 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1289 if (ShiftVal != 0) { in printArithExtend()
1291 markup(O, Markup::Immediate) << "#" << ShiftVal; in printArithExtend()
1297 if (ShiftVal != 0) { in printArithExtend()
1299 markup(O, Markup::Immediate) << "#" << ShiftVal; in printArithExtend()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp482 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
483 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); in getIntMatCost()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h313 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
314 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
328 unsigned &ShiftVal);
329 void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2383 auto ShiftVal = Op.getOperand(1); in LowerShift() local
2412 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1); in LowerShift()
2413 ShiftVal = DAG.getSplatValue(ShiftVal); in LowerShift()
2414 if (!ShiftVal) in LowerShift()
2418 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1); in LowerShift()
2420 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32); in LowerShift()
2437 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal); in LowerShift()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1252 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1257 ShiftVal, SetFlags, WantResult); in emitAddSub()
1274 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1280 ShiftVal, SetFlags, WantResult); in emitAddSub()
1636 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
4657 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4685 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4720 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
4751 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4754 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
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H A DAArch64ISelDAGToDAG.cpp659 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
660 if (ShiftVal > 3) in isWorthFoldingSHL()
916 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
923 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
924 if (ShiftVal > 4) in SelectArithExtendedRegister()
960 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
969 unsigned ShiftVal = 0; in SelectArithUXTXRegister() local
978 ShiftVal = CSD->getZExtValue(); in SelectArithUXTXRegister()
979 if (ShiftVal > 4) in SelectArithUXTXRegister()
1201 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
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H A DAArch64InstrInfo.cpp936 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
937 if (ShiftVal == 0) in isFalkorShiftExtFast()
939 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
963 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
964 return ShiftVal == 0 || in isFalkorShiftExtFast()
965 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
971 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
972 return ShiftVal == 0 || in isFalkorShiftExtFast()
973 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
H A DAArch64TargetTransformInfo.cpp365 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
366 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp781 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
782 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal); in CreateWideLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1750 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchShiftOfShiftedLogic()
1863 ShiftVal = MaybeImmVal->Value.exactLogBase2(); in matchCombineMulToShl()
1864 return (static_cast<int32_t>(ShiftVal) != -1); in matchCombineMulToShl()
1872 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2185 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchCombineShiftToUnmerge()
2186 return ShiftVal >= Size / 2 && ShiftVal < Size; in matchCombineShiftToUnmerge()
2196 assert(ShiftVal >= HalfSize); in applyCombineShiftToUnmerge()
2202 unsigned NarrowShiftAmt = ShiftVal - HalfSize; in applyCombineShiftToUnmerge()
2238 if (ShiftVal == HalfSize) { in applyCombineShiftToUnmerge()
2242 } else if (ShiftVal == Size - 1) { in applyCombineShiftToUnmerge()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2715 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2724 ShiftVal = Amount; in isSimpleShift()
2893 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2896 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2897 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2898 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2904 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2907 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2908 (MaskVal << ShiftVal != 0) && in adjustForTestUnderMask()
2909 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal && in adjustForTestUnderMask()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp401 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
404 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
411 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
H A DInstCombineCompares.cpp2217 const APInt *ShiftVal; in foldICmpShlConstant() local
2218 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
2219 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2257 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2262 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
2278 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2279 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
2283 ReplaceNode(N, getBFE32(false, SDLoc(N), And.getOperand(0), ShiftVal, in SelectS_BFE()
H A DAMDGPUISelLowering.cpp3089 auto ShiftVal = DAG.getConstant(LeadingZeroes, SL, MVT::i32); in lowerCTLZResults() local
3090 NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, ShiftVal); in lowerCTLZResults()
5165 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
5167 BitsFrom, ShiftVal); in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5359 unsigned ShiftVal = 0; in Select() local
5364 ShiftVal = 1; in Select()
5368 ShiftVal = 1; in Select()
5373 ShiftVal = 3; in Select()
5377 ShiftVal = 3; in Select()
5382 ShiftVal = 2; in Select()
5386 ShiftVal = 2; in Select()
5418 SDValue Ops[] = {Move, getI32Imm((32 - (4 + ShiftVal)) & 31, dl), in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp1565 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in upgradeX86ALIGNIntrinsics() local
1574 ShiftVal &= (NumElts - 1); in upgradeX86ALIGNIntrinsics()
1578 if (ShiftVal >= 32) in upgradeX86ALIGNIntrinsics()
1583 if (ShiftVal > 16) { in upgradeX86ALIGNIntrinsics()
1584 ShiftVal -= 16; in upgradeX86ALIGNIntrinsics()
1593 unsigned Idx = ShiftVal + i; in upgradeX86ALIGNIntrinsics()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp389 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
390 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
396 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
H A DX86ISelLowering.cpp6031 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
17978 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
17990 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
30227 if (!ShiftVal) in FindSingleBitChange()
30229 if (ShiftVal->equalsInt(1)) in FindSingleBitChange()
36948 if (ShiftVal.uge(VTBits)) in ComputeNumSignBitsForTargetNode()
36951 if (ShiftVal.uge(Tmp)) in ComputeNumSignBitsForTargetNode()
36962 ShiftVal += Tmp; in ComputeNumSignBitsForTargetNode()
36963 return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); in ComputeNumSignBitsForTargetNode()
47549 if (!ShiftVal) in combineVectorShiftImm()
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H A DX86TargetTransformInfo.cpp5511 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
5512 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1984 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2000 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp15033 if (ShiftVal >= 32) in EmitX86BuiltinExpr()
15038 if (ShiftVal > 16) { in EmitX86BuiltinExpr()
15039 ShiftVal -= 16; in EmitX86BuiltinExpr()
15048 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
15069 ShiftVal &= NumElts - 1; in EmitX86BuiltinExpr()
15073 Indices[i] = i + ShiftVal; in EmitX86BuiltinExpr()
15155 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
15184 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
15211 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
15232 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7449 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local
7452 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
7540 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
7557 ShiftVal = *MaybeShiftVal; in selectArithExtendedRegister()
7558 if (ShiftVal > 4) in selectArithExtendedRegister()
7594 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()