Searched refs:ShiftRight (Results 1 – 5 of 5) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| H A D | RuntimeDyldChecker.cpp | 116 ShiftRight enumerator
183 return std::make_pair(BinOpToken::ShiftRight, Expr.substr(2).ltrim()); in parseBinOpToken()
222 case BinOpToken::ShiftRight: in computeBinOpResult()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1842 SDValue ShiftRight = Op.getOperand(0); in LowerTruncateToBTST() local
1843 return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1), in LowerTruncateToBTST()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4263 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector() local
4266 if (ShiftRight != 0) in insert1BitVector()
4268 DAG.getTargetConstant(ShiftRight, dl, MVT::i8)); in insert1BitVector()
4305 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal; in insert1BitVector() local
4317 DAG.getTargetConstant(ShiftRight, dl, MVT::i8)); in insert1BitVector()
4328 DAG.getTargetConstant(ShiftRight, dl, MVT::i8)); in insert1BitVector()
48655 if (SDValue ShiftRight = combineAndMaskToShift(N, DAG, Subtarget)) in combineAnd() local
48656 return ShiftRight; in combineAnd()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8133 SDValue ShiftRight = in lowerEXTRACT_VECTOR_ELT() local
8135 SDValue Res = DAG.getNode(ISD::AND, DL, XLenVT, ShiftRight, in lowerEXTRACT_VECTOR_ELT()
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| /freebsd-14.2/sys/contrib/dev/acpica/ |
| H A D | changes.txt | 3970 ShiftRight. The actual problem cases seem to be rather unusual in common
4272 Z = X >> Y ShiftRight (X, Y, Z)
4301 X >>= Y ShiftRight (X, Y, X)
11929 Fixed a problem where a ShiftLeft or ShiftRight of more than 64 bits
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