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Searched refs:ShiftOpc (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h27 enum ShiftOpc { enum
44 inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
56 inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
102 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } in getSORegShOp()
400 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
412 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
413 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
H A DARMMCCodeEmitter.cpp248 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1280 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1318 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1533 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1578 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1687 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
H A DARMInstPrinter.cpp52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
404 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
H A DARMInstructionSelector.cpp62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
804 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift() argument
808 MIB.addImm(ShiftOpc); in selectShift()
1060 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); in select()
1062 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
1064 return selectShift(ARM_AM::ShiftOpc::lsl, MIB); in select()
H A DARMFastISel.cpp181 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2698 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2725 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2771 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
H A DARMISelDAGToDAG.cpp92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
544 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
617 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
641 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
763 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
843 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1510 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
3380 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
H A DARMBaseInstrInfo.cpp235 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
H A DARMISelLowering.cpp19800 ARM_AM::ShiftOpc ShOpcVal= in getARMIndexedAddressParts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp798 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
836 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
853 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
882 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp462 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
865 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
875 ARM_AM::ShiftOpc ShiftTy;
885 ARM_AM::ShiftOpc ShiftTy;
892 ARM_AM::ShiftOpc ShiftTy;
3636 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
4137 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
5513 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; in parsePostIdxReg()
5849 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; in parseMemory()
10302 ARM_AM::ShiftOpc ShiftTy; in processInstruction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp1104 auto ShiftOpc = ShrAmtC > ShAmtC ? Shr->getOpcode() : Instruction::Shl; in visitShl() local
1110 Value *NewShift = Builder.CreateBinOp(ShiftOpc, X, ShiftDiffC, "sh.diff"); in visitShl()
H A DInstCombineCompares.cpp7178 unsigned ShiftOpc = ShiftI->getOpcode(); in visitICmpInst() local
7179 if ((ExtOpc == Instruction::ZExt && ShiftOpc == Instruction::LShr) || in visitICmpInst()
7180 (ExtOpc == Instruction::SExt && ShiftOpc == Instruction::AShr)) { in visitICmpInst()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1142 EVT VT, unsigned ShiftOpc, bool MayTransformRotate,
H A DX86ISelLowering.cpp3278 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3297 if (ShiftOpc == ISD::SHL || ShiftOpc == ISD::SRL) { in preferedOpcodeForCmpEqPiecesOfOperand()
3307 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
3310 if (ShiftOpc == ISD::SHL) { in preferedOpcodeForCmpEqPiecesOfOperand()
3335 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
24998 unsigned ShiftOpc; in getTargetVShiftByConstNode() local
25002 ShiftOpc = ISD::SHL; in getTargetVShiftByConstNode()
25005 ShiftOpc = ISD::SRL; in getTargetVShiftByConstNode()
25008 ShiftOpc = ISD::SRA; in getTargetVShiftByConstNode()
29957 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h848 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand() argument
851 return ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1672 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegImmOperand()
1712 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegRegOperand()
2110 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; in DecodeAddrMode2IdxInstruction()
2156 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp3494 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
3504 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LsrImm, DL, VT), in tryBitfieldInsertOpFromOr()
H A DAArch64ISelLowering.cpp14415 unsigned ShiftOpc = IsSigned ? ISD::SRA : ISD::SRL; in LowerAVG() local
14434 return DAG.getNode(ShiftOpc, dl, VT, Add, ConstantOne); in LowerAVG()
14437 SDValue ShiftOpA = DAG.getNode(ShiftOpc, dl, VT, OpA, ConstantOne); in LowerAVG()
14438 SDValue ShiftOpB = DAG.getNode(ShiftOpc, dl, VT, OpB, ConstantOne); in LowerAVG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp996 unsigned ShiftOpc = Op.getOpcode(); in combineShiftToAVG() local
1008 switch (ShiftOpc) { in combineShiftToAVG()
H A DDAGCombiner.cpp12582 unsigned ShiftOpc = ShiftOrRotate.getOpcode(); in visitSETCC() local
12592 ShiftOpc == ISD::SHL ? (~*AndCMask).isMask() : AndCMask->isMask(); in visitSETCC()
12597 OpVT, ShiftOpc, ShiftCAmt->isPowerOf2(), *ShiftCAmt, AndCMask); in visitSETCC()
12599 if (CanTransform && NewShiftOpc != ShiftOpc) { in visitSETCC()