| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 784 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
785 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
786 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 983 unsigned ShiftOp; in PromoteIntRes_ADDSUBSHLSAT() local
988 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
991 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
1009 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
1054 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX() local
1055 return DAG.getNode(ShiftOp, dl, PromotedType, Result, in PromoteIntRes_MULFIX()
4584 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
4586 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4587 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
4589 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| H A D | DAGCombiner.cpp | 2675 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2679 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2684 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2685 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
6872 if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse()) in foldLogicOfShifts()
6876 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6886 SDValue X1 = ShiftOp.getOperand(0); in foldLogicOfShifts()
6887 SDValue Y = ShiftOp.getOperand(1); in foldLogicOfShifts()
8720 if (!ShiftOp) in calculateByteProvider()
8723 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
[all …]
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| H A D | SelectionDAGBuilder.cpp | 3076 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
3085 ShiftOp, DAG.getConstant(llvm::countr_zero(B.Mask), dl, VT), in visitBitTestCase()
3091 ShiftOp, DAG.getConstant(llvm::countr_one(B.Mask), dl, VT), ISD::SETNE); in visitBitTestCase()
3095 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1984 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1985 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 2110 Instruction::BinaryOps ShiftOp = in foldBinOpOfDisplacedShifts() local
2112 if (ShiftOp != Op1Inst->getOpcode()) in foldBinOpOfDisplacedShifts()
2116 if (I.getOpcode() == Instruction::Add && ShiftOp != Instruction::Shl) in foldBinOpOfDisplacedShifts()
2120 I.getOpcode(), ShiftedC1, Builder.CreateBinOp(ShiftOp, ShiftedC2, AddC)); in foldBinOpOfDisplacedShifts()
2121 return BinaryOperator::Create(ShiftOp, NewC, ShAmt); in foldBinOpOfDisplacedShifts()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 11578 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateSrcByte() local
11579 if (!ShiftOp) in calculateSrcByte()
11582 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateSrcByte()
11662 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(2)); in calculateByteProvider() local
11663 if (!ShiftOp || Op.getValueType().isVector()) in calculateByteProvider()
11686 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
11687 if (!ShiftOp) in calculateByteProvider()
11690 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
11711 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
11712 if (!ShiftOp) in calculateByteProvider()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3328 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3373 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 2353 auto ShiftOp = [&](const APInt &Lhs, const APInt &Rhs) { in isNonZeroShift() local
2388 if (!ShiftOp(KnownVal.One, MaxShift).isZero()) in isNonZeroShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7770 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; in lowerSMULH_UMULH() local
7773 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 207 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
211 setOperationAction(ShiftOp , MVT::i8 , Custom); in X86TargetLowering()
212 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
213 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction); in X86TargetLowering()
215 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction); in X86TargetLowering()
49547 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
49548 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
49552 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 21624 SDValue ShiftOp = Index.getOperand(1); in foldIndexIntoBase() local
21626 if (auto Shift = DAG.getSplatValue(ShiftOp)) in foldIndexIntoBase()
21632 Add.getOperand(0), ShiftOp); in foldIndexIntoBase()
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