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Searched refs:ShiftLHS (Results 1 – 4 of 4) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp850 MachineInstr *ShiftLHS = in getCmpOperandFoldingProfit() local
856 if (IsSupportedExtend(*ShiftLHS)) in getCmpOperandFoldingProfit()
H A DAArch64InstructionSelector.cpp7444 MachineOperand &ShiftLHS = ShiftInst->getOperand(1); in selectShiftedRegister() local
7445 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp30027 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate() local
30041 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(4, DL, VT)), in LowerRotate()
30051 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(2, DL, VT)), in LowerRotate()
30061 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(1, DL, VT)), in LowerRotate()
53216 SDValue ShiftLHS = Src.getOperand(0); in combineMOVMSK() local
53221 ShiftLHS = DAG.getBitcast(ShiftVT, ShiftLHS); in combineMOVMSK()
53224 ShiftLHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT, in combineMOVMSK()
53225 ShiftLHS, ShiftAmt, DAG); in combineMOVMSK()
53228 ShiftLHS = DAG.getBitcast(SrcVT, ShiftLHS); in combineMOVMSK()
53230 SDValue Res = DAG.getNode(ISD::XOR, DL, SrcVT, ShiftLHS, ShiftRHS); in combineMOVMSK()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16368 SDValue ShiftLHS = N->getOperand(0); in isDesirableToCommuteWithShift() local
16374 if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) && in isDesirableToCommuteWithShift()
16375 isa<ConstantSDNode>(ShiftLHS.getOperand(1))) { in isDesirableToCommuteWithShift()
16376 uint64_t TruncMask = ShiftLHS.getConstantOperandVal(1); in isDesirableToCommuteWithShift()
16378 SDValue AndLHS = ShiftLHS.getOperand(0); in isDesirableToCommuteWithShift()