| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
185 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
188 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
560 .addImm(ShiftImm); in expandAtomicBinOpSubword()
563 .addImm(ShiftImm); in expandAtomicBinOpSubword()
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| H A D | MipsISelLowering.cpp | 1650 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
1652 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1653 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 214 uint64_t ShiftImm, bool SetFlags = false,
252 unsigned RHSReg, uint64_t ShiftImm);
1343 unsigned ShiftImm; in emitAddSub_ri() local
1345 ShiftImm = 0; in emitAddSub_ri()
1347 ShiftImm = 12; in emitAddSub_ri()
1376 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1393 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1418 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
1434 if (ShiftImm >= 4) in emitAddSub_rx()
1462 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
[all …]
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| H A D | AArch64ISelDAGToDAG.cpp | 2395 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
2396 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
2397 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg()
2401 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg()
2406 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg()
2407 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg()
2526 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
2528 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt()
2534 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
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| H A D | AArch64ISelLowering.cpp | 21066 unsigned ShiftImm = N->getConstantOperandVal(1); in performVectorShiftCombine() local
21067 assert(OpScalarSize > ShiftImm && "Invalid shift imm"); in performVectorShiftCombine()
21073 if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm) in performVectorShiftCombine()
21076 APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm); in performVectorShiftCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 876 unsigned ShiftImm; member
888 unsigned ShiftImm; member
894 unsigned ShiftImm; member
2559 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands()
3643 Op->RegShiftedReg.ShiftImm = ShiftImm; in CreateShiftedRegister()
3655 Op->RegShiftedImm.ShiftImm = ShiftImm; in CreateShiftedImmediate()
3808 Op->Memory.ShiftImm = ShiftImm; in CreateMem()
3824 Op->PostIdxReg.ShiftImm = ShiftImm; in CreatePostIdxReg()
3963 << PostIdxReg.ShiftImm; in print()
5514 unsigned ShiftImm = 0; in parsePostIdxReg() local
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2783 unsigned ShiftImm; in SelectShift() local
2786 ShiftImm = CI->getZExtValue(); in SelectShift()
2790 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift()
2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 941 unsigned Size, ShiftImm; in getMVEShiftImmOpValue() local
958 ShiftImm = MI.getOperand(OpIdx).getImm(); in getMVEShiftImmOpValue()
959 return Size + ShiftImm; in getMVEShiftImmOpValue()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1844 std::optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local
1845 if (!ShiftImm) in getVectorSHLImm()
1848 int64_t Imm = *ShiftImm; in getVectorSHLImm()
2389 int64_t ShiftImm; in earlySelect() local
2394 m_GOr(m_OneNonDBGUse(m_GShl(m_Reg(ShiftSrc), m_ICst(ShiftImm))), in earlySelect()
2398 if (ShiftImm > Size || ((1ULL << ShiftImm) - 1ULL) != uint64_t(MaskImm)) in earlySelect()
2401 int64_t Immr = Size - ShiftImm; in earlySelect()
2402 int64_t Imms = Size - ShiftImm - 1; in earlySelect()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 832 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local
836 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; in simplifyCode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 4349 int64_t ShiftImm; in matchBitfieldExtractFromSExtInReg() local
4352 m_OneNonDBGUse(m_any_of(m_GAShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)), in matchBitfieldExtractFromSExtInReg()
4353 m_GLShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)))))) in matchBitfieldExtractFromSExtInReg()
4355 if (ShiftImm < 0 || ShiftImm + Width > Ty.getScalarSizeInBits()) in matchBitfieldExtractFromSExtInReg()
4359 auto Cst1 = B.buildConstant(ExtractTy, ShiftImm); in matchBitfieldExtractFromSExtInReg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 6705 const APInt &ShiftImm = N2C->getAPIntValue(); in getNode() local
6706 return getVScale(DL, VT, MulImm << ShiftImm); in getNode()
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