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Searched refs:ShiftBits (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp100 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType; in getVecExtParmsType() local
111 XCOFF::TracebackTable::ParmTypeIsVectorCharBit >> ShiftBits; in getVecExtParmsType()
117 XCOFF::TracebackTable::ParmTypeIsVectorShortBit >> ShiftBits; in getVecExtParmsType()
123 XCOFF::TracebackTable::ParmTypeIsVectorIntBit >> ShiftBits; in getVecExtParmsType()
129 XCOFF::TracebackTable::ParmTypeIsVectorFloatBit >> ShiftBits; in getVecExtParmsType()
145 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType; in getParmsType() local
159 XCOFF::TracebackTable::ParmTypeIsFixedBits >> ShiftBits; in getParmsType()
171 XCOFF::TracebackTable::ParmTypeIsFloatingBits >> ShiftBits; in getParmsType()
178 XCOFF::TracebackTable::ParmTypeIsDoubleBits >> ShiftBits; in getParmsType()
188 XCOFF::TracebackTable::ParmTypeIsVectorBits >> ShiftBits; in getParmsType()
H A DPPCRegisterInfo.cpp1028 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore() local
1031 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
1190 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore() local
1195 .addImm(ShiftBits ? 32 - ShiftBits : 0) in lowerCRBitRestore()
1196 .addImm(ShiftBits) in lowerCRBitRestore()
1197 .addImm(ShiftBits); in lowerCRBitRestore()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp464 unsigned ShiftBits = Offset.getBitWidth() - IndexSize; in adjustToIndexSize() local
465 if (ShiftBits != 0) { in adjustToIndexSize()
466 Offset <<= ShiftBits; in adjustToIndexSize()
467 Offset.ashrInPlace(ShiftBits); in adjustToIndexSize()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp5075 unsigned ShiftBits = AndRHSC.countr_zero(); in SimplifySetCC() local
5076 if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { in SimplifySetCC()
5079 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
5080 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); in SimplifySetCC()
5092 unsigned ShiftBits; in SimplifySetCC() local
5096 ShiftBits = C1.countr_one(); in SimplifySetCC()
5100 ShiftBits = C1.countr_zero(); in SimplifySetCC()
5102 NewC.lshrInPlace(ShiftBits); in SimplifySetCC()
5103 if (ShiftBits && NewC.getSignificantBits() <= 64 && in SimplifySetCC()
5105 !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) { in SimplifySetCC()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4806 unsigned ShiftBits = llvm::countl_zero(Mask); in getARMCmp() local
4807 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) { in getARMCmp()
4808 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32); in getARMCmp()
4810 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32); in getARMCmp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4230 SDValue ShiftBits = DAG.getTargetConstant(SubVecNumElems, dl, MVT::i8); in insert1BitVector() local
4233 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
4234 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
4289 SDValue ShiftBits = DAG.getTargetConstant(NumElems - IdxVal, dl, MVT::i8); in insert1BitVector() local
4290 Vec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
4291 Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
30373 unsigned ShiftBits = SI->getType()->getPrimitiveSizeInBits(); in emitBitTestAtomicRMWIntrinsic() local
30375 Builder.CreateAnd(SI, Builder.getIntN(ShiftBits, ShiftBits - 1)); in emitBitTestAtomicRMWIntrinsic()