| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVBaseInfo.h | 255 for (unsigned ShiftAmount = 0; ShiftAmount < 32; ShiftAmount += 8) { in getSPIRVStringOperand() local
256 char c = (Imm >> ShiftAmount) & 0xff; in getSPIRVStringOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 378 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
382 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
413 ShiftAmount = 0; in LowerShifts()
418 ShiftAmount = 0; in LowerShifts()
423 ShiftAmount = 0; in LowerShifts()
428 ShiftAmount = 0; in LowerShifts()
434 ShiftAmount = 0; in LowerShifts()
440 ShiftAmount = 0; in LowerShifts()
445 ShiftAmount = 0; in LowerShifts()
479 if (4 <= ShiftAmount && ShiftAmount < 8) in LowerShifts()
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| H A D | AVRShiftExpand.cpp | 94 Value *ShiftAmount = Builder.CreateTrunc(BI->getOperand(1), Int8Ty); in expand() local
98 Value *Cmp1 = Builder.CreateICmpEQ(ShiftAmount, Int8Zero); in expand()
105 ShiftAmountPHI->addIncoming(ShiftAmount, BB); in expand()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 108 int ShiftAmount = 0; in generateInstSeqImpl() local
113 ShiftAmount = llvm::countr_zero((uint64_t)Val); in generateInstSeqImpl()
114 Val >>= ShiftAmount; in generateInstSeqImpl()
118 if (ShiftAmount > 12 && !isInt<12>(Val)) { in generateInstSeqImpl()
121 ShiftAmount -= 12; in generateInstSeqImpl()
127 ShiftAmount -= 12; in generateInstSeqImpl()
146 if (ShiftAmount) { in generateInstSeqImpl()
148 Res.emplace_back(Opc, ShiftAmount); in generateInstSeqImpl()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | DivisionByConstantInfo.h | 24 unsigned ShiftAmount; ///< shift amount member
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| /freebsd-14.2/contrib/llvm-project/clang/lib/AST/Interp/ |
| H A D | IntegralAP.h | 259 unsigned ShiftAmount = B.V.getZExtValue(); in shiftRight() local
261 *R = IntegralAP(A.V.ashr(ShiftAmount)); in shiftRight()
263 *R = IntegralAP(A.V.lshr(ShiftAmount)); in shiftRight()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 177 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
184 .addImm(ShiftAmount); in emitPrologue()
187 .addImm(ShiftAmount); in emitPrologue()
194 .addImm(ShiftAmount); in emitPrologue()
197 .addImm(ShiftAmount); in emitPrologue()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 3076 if (ShiftAmount == 0) in getVLENFactoredAmount()
3080 .addImm(ShiftAmount) in getVLENFactoredAmount()
3088 uint32_t ShiftAmount; in getVLENFactoredAmount() local
3091 ShiftAmount = Log2_64(NumOfVReg / 9); in getVLENFactoredAmount()
3101 if (ShiftAmount) in getVLENFactoredAmount()
3104 .addImm(ShiftAmount) in getVLENFactoredAmount()
3115 .addImm(ShiftAmount) in getVLENFactoredAmount()
3126 .addImm(ShiftAmount) in getVLENFactoredAmount()
3146 for (uint32_t ShiftAmount = 0; NumOfVReg >> ShiftAmount; ShiftAmount++) { in getVLENFactoredAmount() local
3148 if (ShiftAmount) in getVLENFactoredAmount()
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| H A D | RISCVRegisterInfo.cpp | 323 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVSPILL() local
324 if (ShiftAmount != 0) in lowerVSPILL()
327 .addImm(ShiftAmount); in lowerVSPILL()
400 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVRELOAD() local
401 if (ShiftAmount != 0) in lowerVRELOAD()
404 .addImm(ShiftAmount); in lowerVRELOAD()
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| H A D | RISCVFrameLowering.cpp | 673 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
678 .addImm(ShiftAmount) in emitPrologue()
682 .addImm(ShiftAmount) in emitPrologue()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Support/ |
| H A D | DivisionByConstantInfo.cpp | 63 Retval.ShiftAmount = P - D.getBitWidth(); // resulting shift in get()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.h | 48 unsigned ShiftAmount) const;
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| H A D | MipsTargetStreamer.h | 144 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| H A D | MipsSEISelDAGToDAG.cpp | 283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
297 const Align Alignment(1ULL << ShiftAmount); in selectAddrFrameIndexOffset()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 274 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
276 if (ShiftAmount >= 32) { in emitDSLL()
277 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
281 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| H A D | MipsMCCodeEmitter.h | 185 template <unsigned ShiftAmount = 0>
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| H A D | MipsMCCodeEmitter.cpp | 742 template <unsigned ShiftAmount>
753 OffBits >>= ShiftAmount; in getMemEncoding()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 968 uint64_t ShiftAmount = N->getConstantOperandVal(1); in LowerShifts() local
973 if (ShiftAmount >= 8) { in LowerShifts()
993 ShiftAmount -= 8; in LowerShifts()
996 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
1000 ShiftAmount -= 1; in LowerShifts()
1003 while (ShiftAmount--) in LowerShifts()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 433 unsigned ShiftAmount; member
614 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
972 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
2237 unsigned ShiftAmount = 0, in CreateReg() argument
2245 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
2256 unsigned ShiftAmount = 0, in CreateVectorReg() argument
2347 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
3374 int64_t ShiftAmount = getTok().getIntVal(); in tryParseImmWithOptionalShift() local
3376 if (ShiftAmount < 0) in tryParseImmWithOptionalShift()
3381 if (ShiftAmount == 0 && Imm != nullptr) { in tryParseImmWithOptionalShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 6534 auto *C = dyn_cast<Constant>(ShiftAmount); in shiftAmountKnownInRange()
8580 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
8582 ShiftAmount = C->countr_zero(); in setLimitsForBinOp()
8586 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
8589 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
8601 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
8603 ShiftAmount = C->countr_zero(); in setLimitsForBinOp()
8604 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
8618 unsigned ShiftAmount = C->countl_one() - 1; in setLimitsForBinOp() local
8619 Lower = C->shl(ShiftAmount); in setLimitsForBinOp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1276 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1278 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1279 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| H A D | TargetLowering.cpp | 2292 unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ; in SimplifyDemandedBits() local
6202 magics.ShiftAmount = 0; in BuildSDIV()
7482 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
7483 SDValue Shift = DAG.getShiftAmountConstant(ShiftAmount, VT, dl); in expandMUL_LOHI()
9333 SDValue ShiftAmount = in scalarizeVectorLoad() local
9418 SDValue ShiftAmount = in scalarizeVectorStore() local
9421 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); in scalarizeVectorStore()
9595 SDValue ShiftAmount = in expandUnalignedLoad() local
9598 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in expandUnalignedLoad()
9709 SDValue ShiftAmount = DAG.getConstant( in expandUnalignedStore() local
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| H A D | LegalizeIntegerTypes.cpp | 999 SDValue ShiftAmount = in PromoteIntRes_ADDSUBSHLSAT() local
1002 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
1005 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
1009 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
4178 SDValue ShiftAmount = DAG.getShiftAmountConstant(Scale % NVTSize, NVT, dl); in ExpandIntRes_MULFIX() local
4180 ShiftAmount); in ExpandIntRes_MULFIX()
4182 ShiftAmount); in ExpandIntRes_MULFIX()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCasts.cpp | 411 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
413 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
424 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1909 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
1910 if (ShiftAmount == Power) in factorOutPowerOf2()
1912 Ops[1] = CurDAG->getConstant(ShiftAmount - Power, in factorOutPowerOf2()
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