Searched refs:Shift1 (Results 1 – 7 of 7) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 732 uint64_t Shift1 = 0, Shift2 = 0; in foldLoadsRecursive() local
734 Shift1 = ShAmt1->getZExtValue(); in foldLoadsRecursive()
752 if ((Shift2 - Shift1) != ShiftDiff || (Offset2 - Offset1) != PrevSize) in foldLoadsRecursive()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 743 bool Shift1 = mi_match( in selectG_BUILD_VECTOR() local
747 if (Shift0 && Shift1) { in selectG_BUILD_VECTOR()
751 } else if (Shift1) { in selectG_BUILD_VECTOR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 2044 const APInt *Shift1, *Shift2; in simplifyAndCommutative() local
2045 if (match(Op0, m_Shl(m_Value(X), m_APInt(Shift1))) && in simplifyAndCommutative()
2049 Shift1->uge(*Shift2)) in simplifyAndCommutative()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1795 Register Shift1 = in applyShiftOfShiftedLogic() local
1812 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5118 def Shift1 {
5124 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
5125 (AND Shift1.Left, MaskValues.Hi1));
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 7612 SDValue Shift1 = N1.getOperand(0); in matchBSwapHWordOrAndAnd() local
7613 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
7616 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1)); in matchBSwapHWordOrAndAnd()
7621 if (Shift0.getOperand(0) != Shift1.getOperand(0)) in matchBSwapHWordOrAndAnd()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29269 SDValue Shift1 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
29273 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
46580 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
46584 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
46918 SDValue Shift1 = in combineMul() local
46924 NewMul = DAG.getNode(*Opc, DL, VT, Shift1, Shift2); in combineMul()
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