| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift() argument
54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
59 O << getShiftOpcStr(ShOpc); in printRegImmShift()
61 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
404 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand() local
405 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand()
406 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
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| H A D | ARMMCCodeEmitter.cpp | 248 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
249 switch (ShOpc) { in getShiftOp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 872 unsigned ShOpc) { in foldBinOpShiftWithShift() argument
873 assert(ShOpc != Instruction::AShr); in foldBinOpShiftWithShift()
875 ShOpc == Instruction::Shl; in foldBinOpShiftWithShift()
878 auto GetInvShift = [](unsigned ShOpc) { in foldBinOpShiftWithShift() argument
879 assert(ShOpc != Instruction::AShr); in foldBinOpShiftWithShift()
884 unsigned ShOpc, Constant *CMask, in foldBinOpShiftWithShift()
892 if (!IsCompletelyDistributable(BinOpc1, BinOpc2, ShOpc)) in foldBinOpShiftWithShift()
929 unsigned ShOpc = IY->getOpcode(); in foldBinOpShiftWithShift() local
930 if (ShOpc != IX->getOpcode()) in foldBinOpShiftWithShift()
943 if (ShOpc == Instruction::AShr) { in foldBinOpShiftWithShift()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 672 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI; in tryShrinkShlLogicImm() local
678 CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0), in tryShrinkShlLogicImm()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6482 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; in lowerRotate() local
6492 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
6501 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3381 SDValue ShOpc = in tryV6T2BitfieldExtractOp() local
3384 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp()
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| H A D | ARMBaseInstrInfo.cpp | 235 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress() local
236 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
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| H A D | ARMISelLowering.cpp | 6699 unsigned ShOpc = N->getOpcode(); in Expand64BitShift() local
6715 if (ShOpc == ISD::SRL) { in Expand64BitShift()
6724 } else if (ShOpc == ISD::SRA) in Expand64BitShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 7950 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT() local
7960 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
7968 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 29360 unsigned ShOpc = ConstantAmt ? Opc : X86OpcV; in LowerShift() local
29361 SDValue R0 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt0)); in LowerShift()
29362 SDValue R1 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt1)); in LowerShift()
29363 SDValue R2 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt2)); in LowerShift()
29364 SDValue R3 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt3)); in LowerShift()
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